- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299581 > ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680 PDF資料下載
參數(shù)資料
| 型號(hào)： | ORLI10G-1BM680 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, MULTILAYER, BGA-680 |
| 文件頁(yè)數(shù)： | 9/74頁(yè) |
| 文件大?。?/td> | 1411K |
| 代理商： | ORLI10G-1BM680 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)
Agere Systems Inc.
17
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
ORLI10G Overview (continued)
Transmit Path
In the transmit path, the ORLI10G embedded core can
be broken down into three sections: the multiplexer, the
transmit side onboard PLLs, and the high-speed line
interface. Note that both transmit and receive PLLs are
in addition to the four programmable PLLs (PPLLs) in
the FPGA portion of the ORLI10G.
MUX
The multiplexer takes data from the FPGA logic and
multiplexes the data to rates for transfer by the high-
speed line interface. The multiplexer supports two
modes of operation:
s
Multiplex-by-8
The multiplexer converts the incoming 128 bits of data
at 78 Mbits/s to 83 Mbits/s to 16 bits at 622 Mbits/s to
667 Mbits/s. The incoming transmit reference clock is
divided by 8.
s
Multiplex-by-4
10G (or single channel): The multiplexer converts the
incoming 64 bits of data at 156 Mbits/s to 166 Mbits/s
to 16 bits at 622 Mbits to 667 Mbits/s. The transmit ref-
erence clock is divided by 4.
Onboard Transmit PLLs
The function of the onboard PLLs is to align the system
data with the line data which will be at a slightly higher
rate owing to the addition of the overhead bits. There
are two PLLs on the transmit path. The input to the first
PLL, TX1_PLL (see Figure 4), is the divided down
transmit reference clock from the multiplexer. The
TX1_PLL generates a clock with a user-defined fre-
quency ratio of M/N to the divided clock. This clock
would generally be used to compensate for different
data rates due to overhead bits. M and N can indepen-
dently be set from 1 to 40.
The TX2_PLL also takes its input reference from the
divided down reference clock and is used to provide a
balanced divided clock across the FPGA-embedded
core interface.
Both PLLs have delay loops which compensate for
routing delays to the embedded core/FPGA logic inter-
face for minimum clock skew.
In addition, the user can specify an additional skew on
each clock in increments of 1/8 the clock period.
The selection of the MUX width (and corresponding
clock division value), the TX1_PLL M and N values,
and the additional skew for TX1_PLL and TX2_PLL are
specified by the user in a GUI interface provided in the
ORLI10G deisng kit.
A detailed block diagram of the transmit path in shown
in Figure 4.
Line Interface
In the transmit path, 16-bit data and associated clocks
are outputs from the line interface. Typical data rates
are expected to range from 622 Mbits/s to 667 Mbits/s
for most applications. The 16-bit LVDS output data bus
is actually composed of four 4-bit data buses with one
clock for each 4-bit data bus. On the transmit side,
these clocks will all be synchronized. The ORLI10G
uses LVDS (low-voltage differential signaling)
drivers/receivers which are intended to provide point-
to-point connection between the ORLI10G and optical
transceiver (MUX/deMUX) parts. The LVDS drivers are
hot-swap compatible and can connect to other vendor’s
LVDS I/O buffers. The LVDS drivers are terminated with
a 100
resistor to improve performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORLI10G-1BM416I | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-1BMN416I | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-1BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORLI10G-2BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。