參數(shù)資料
型號(hào)： ORLI10G-1BM416I
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, MULTILAYER, BGA-416
文件頁(yè)數(shù)： 7/74頁(yè)
文件大?。?/td> 1411K
代理商： ORLI10G-1BM416I
Agere Systems Inc.
15
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
ORLI10G Overview (continued)
Receive Path
In the receive path, the ORLI10G embedded core can
be broken down into three sections: the high-speed line
interface, the demultiplexer, and the receive-side on-
board PLLs. Note that both transmit and receive PLLs
are in addition to the four programmable PLLs (PPLLs)
in the FPGA portion of the ORLI10G.
Line Interface
In the receive path, 16-bit data and associated clocks
are inputs to the line interface. Typical data rates are
expected to range from 622 Mbits/s to 667 Mbits/s for
most applications. The 16-bit LVDS input data bus is
actually composed of four 4-bit data busses with one
clock for each four bit data bus. In the 10G mode, all
four input clocks are tied together internal to the device
and driven by the lowest-order input clock. In 2.5G
mode, the four clocks may be asynchronous to each
other. The ORLI10G uses LVDS (low voltage differen-
tial signaling) drivers/receivers which are intended to
provide point-to-point connection between the
ORLI10G and optical transceiver (MUX/deMUX) parts.
The LVDS inputs are hot-swap compatible and can
connect to other vendor’s LVDS I/O buffers. The LVDS
inputs are terminated with a 100
resistor to improve
performance.
DeMUX
The demultiplexer takes the high-speed line data and
clocks and converts the data and clock to rates appro-
priate for transfer to the FPGA logic. The demultiplexer
supports two modes of operation:
s
Divide-by-8
10G (or single channel): The demultiplexer converts
the incoming 16 bits of data at 622 Mbits/s to
667 Mbits/s to 128 bits at 78 Mbits/s to 83 Mbits/s. The
incoming clocks are divided by 8.
2.5G (or quad channel): The demultiplexer converts the
incoming four bits of data at 622 Mbits/s to
667 Mbits/s to 32 bits at 78 Mbits/s to 83 Mbits/s. The
associated clock is also divided by 8. This is repeated
four times with each 4-bit data/clock group assumed to
be asynchronous to the others.
s
Divide-by-4
10G (or single channel): The demultiplexer converts
the incoming 16 bits of data at 622 Mbits/s to
667 Mbits/s to 64 bits at 156 Mbits/s to 166 Mbits/s.
The incoming clocks are divided by 4.
2.5G (or quad channel): The demultiplexer converts the
incoming four bits of data at 622 Mbits/s to
667 Mbits/s to 16 bits at 156 Mbits/s to 166 Mbits/s.
The associated clock is also divided by 4. This is
repeated four times with each 4-bit data/clock group
assumed to be asynchronous to the others.
Onboard Receive PLLs
The function of the onboard PLLs is to align the system
data with the line data which will be at a slightly higher
rate owing to the addition of the overhead bits. There
are two PLLs on the receive path. The input to the first
PLL, RX1_PLL (see Figure 3), is the divided down low-
est-order clock from the demultiplexer. The RX1_PLL
generates a clock with a user-defined frequency ratio of
M/N to the divided clock. This clock would generally be
used to compensate for different data rates due to over-
head bits. M and N can independently be set from 1 to
40.
The RX2_PLL also takes its input from the divided
down clock and is used to provide a balanced divided
clock across the FPGA-embedded core interface.
Both PLLs have delay loops which compensate for
routing delays to the embedded core/FPGA logic inter-
face for minimum clock skew.
In addition, the user can specify an additional skew on
each clock in increments of 1/8 the clock period.
The selection of the deMUX width (and corresponding
clock division value), the RX1_PLL M and N values,
and the additional skew for RX1_PLL and RX2_PLL
are specified by the user in a GUI interface provided in
the ORLI10G design kit.
A detailed block diagram of the receive path in shown
相關(guān)PDF資料
PDF描述
ORLI10G-1BM416 FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BM680I FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORLI10G-1BM416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
ORLI10G-1BMN416I FPGA, 1296 CLBS, 380000 GATES, PBGA416
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