參數(shù)資料
型號(hào)： ORLI10G-1BM416I
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, MULTILAYER, BGA-416
文件頁數(shù)： 18/74頁
文件大?。?/td> 1411K
代理商： ORLI10G-1BM416I
Agere Systems Inc.
25
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
ORLI10G Multiplexer Detail
The multiplexer module converts the incoming 128 bits of data at 78 MHz/83 MHz or 64 bits of data at
156 MHz/166 MHz into 16 bits of data at 622 MHz/666 MHz. It has been implemented as two stages. The first
stage deinterleaves each incoming byte into a different byte stream that can be serially output on the output data
pins. The second stage outputs these bytes into 16 bits or four groups of 4 bits depending upon the mode of oper-
ation. Functionally, the multiplexer architecture consists of three blocks: the parallel-to-serial conversion, the
counters, and the deinterleaving.
For 2.5G divide-by-8 mode, the first stage of the line interface module deinterleaves each incoming byte of data
into a different byte stream on the 78 MHz/83 MHz clock. This data is first registered on the rising edge of the
622 MHz/666 MHz clock input. The data is registered at a time when it is safe to do so; in this case, it is nearer to
the falling edge of the 78 MHz/83 MHz clock. The enable inputs are used to transfer data from the low-speed clock
to the high-speed clock as well as synchronizing the counters of parallel-to-serial conversion which are running at
the high-speed clock. The block diagram is shown in Figure 10.
For 2.5G divide-by-4 mode, the first stage of the line interface module deinterleaves each incoming byte of data
into a different byte stream on the 156 MHz/166 MHz clock. This data is first registered on the rising edge of the
622 MHz/666 MHz clock input. The data is registered at a time when it is safe to do so; in this case, it is nearer to
the falling edge of the 156 MHz/166 MHz clock. The enable inputs are used to transfer data from the low-speed
clock to the high-speed clock as well as synchronizing the counters of parallel-to-serial conversion which are run-
ning at the high-speed clock. The block diagram is also shown in Figure 10.
In 2.5G modes, the enable inputs are assumed to be four clock cycles wide and are shortened internally. They
have to be synchronous to their corresponding clock. In single channel operation, the four groups of 4 bits must
have relationship to the slice zero clock. In single-channel mode, all the enable inputs are to be identical (gener-
ated from the slice zero clock).
In 10G mode the enable signal in generated internally from the transmit reference clock.
Figure 11 shows the valid data input bits to the multiplexer in each of the four modes (divide-by-8, 10G and 2.5G
modes, and divide-by-4, 10G and 2.5G modes). Figure 12—Figure 15 show the multiplexer input transmit refer-
ence clock, data, enable, and clock waveforms and output clock and data waveforms for all four modes.
1336(F)
Figure 10. Multiplexer Interface
DEINTERLEAVE
128
P2S
DAT_IN
CLK8_IN
ENB
CLK_IN
DAT_OUT
CLK_OUT
COUNTERS
ENB_INT
COUNT
81
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ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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