參數(shù)資料
型號: ORLI10G-1BM416I
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝: PLASTIC, MULTILAYER, BGA-416
文件頁數(shù): 36/74頁
文件大小: 1411K
代理商: ORLI10G-1BM416I
Agere Systems Inc.
41
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100
differential impedance, as shown below. External resistors are
not required. The differential driver and receiver buffers include termination resistors inside the device package as
shown in Figure 24 below.
5-8703(F)
Figure 24. LVDS Driver and Receiver and Associated Internal Components
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an
unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to
ground, the LVDS driver will not suffer permanent damage. Figure 25 illustrates the terms associated with LVDS
driver and receiver pairs.
5-8704(F)
Figure 25. LVDS Driver and Receiver
5-8705(F)
Figure 26. LVDS Driver
LVDS DRIVER
50
50
LVDS RECEIVER
CENTER TAP
DEVICE PINS
100
EXTERNAL
VGPD
VOA
VOB
VIA
VIB
A
B
AA
BB
DRIVER
INTERCONNECT
RECEIVER
VOA
A
VOB
B
CA
CB
RLOAD
VOD = (VOA – VOB)
V
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