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| 型號(hào)： | ORCAORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁(yè)數(shù)： | 66/90頁(yè) |
| 文件大小： | 1915K |
| 代理商： | ORCAORT4622 |
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ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
66
L Lucent Technologies Inc.
Pin Information
(continued)
Table 41. Embedded Core/FPGA Interface Signal Description
(continued)
Pin Name
I/O
Description
toh_rxd
rx_toh_ck_en
rx_toh_fp
toh_ck_fp_en
I
I
I
I
TOH serial link for receiver D.
RX TOH serial link clock enable.
RX TOH serial link frame pulse.
A soft register bit available to enable RX TOH clock and frame
pulse.
RX TOH enable, soft register. "AND" output of resistor channel
A enable and hi-z control of TOH data output A.
CPU interface data bus.
CPU interface data bus.
CPU interface address bus.
CPU interface read/write.
Chip select.
Interrupt.
System frame pulse for transmitter section.
Line frame pulse for receiver section.
System clock (77.76 MHz).
Protection switching control signal.
Protection switching control signal.
During powerup and FPGA configuration sequence, the
core_ready is held low. At the end of FPGA configuration, the
core_ready will be held low for six clock (sys_clk) cycles and
then go active-high. Flag indicates that the embedded core is
out of its reset state.
The alignment FIFO synchronizes and locates the data frames
and outputs an optimal frame pulse for the four arriving data
streams.
77.76 MHz recovered clock for channel A.
77.76 MHz recovered clock for channel B.
77.76 MHz recovered clock for channel C.
77.76 MHz recovered clock for channel D.
Bit stream selection for microprocessor interface selection.
A 0 indicates the microprocessor interface on the core side is
selected. A 1 selects the CPU interface from the FPGA side.
toh_en_a
I
cpu_data_tx<7:0>
cpu_data_rx<7:0>
cpu_addr<6:0>
cpu_rd_wr_n
cpu_cs_n
cpu_int_n
sys_fp
line_fp
fpga_sysclk
prot_sw_a
prot_sw_c
core_ready
O
I
O
O
O
I
O
O
I
O
O
I
fifosync_fp
I
cdr_clk_a
cdr_clk_b
cdr_clk_c
cdr_clk_d
rb_mp_sel
I
I
I
I
I
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