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參數(shù)資料
| 型號(hào)： | ORCAORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁(yè)數(shù)： | 63/90頁(yè) |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
63
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information
(continued)
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary.
Table 40. FPSC Function Pin Description
Symbol
I/O
Description
HSI LVDS Pins
sts_ina
sts_inan
sts_inb
sts_inbn
sts_inc
sts_incn
sts_ind
sts_indn
sts_outa
sts_outan
sts_outb
sts_outbn
sts_outc
sts_outcn
sts_outd
sts_outdn
ctap_refa
ctap_refb
ctap_refc
ctap_refd
I
I
I
I
I
I
I
I
LVDS input receiver A.
LVDS input receiver A.
LVDS input receiver B.
LVDS input receiver B.
LVDS input receiver C.
LVDS input receiver C.
LVDS input receiver D.
LVDS input receiver D.
LVDS output receiver A.
LVDS output receiver A.
LVDS output receiver B.
LVDS output receiver B.
LVDS output receiver C.
LVDS output receiver C.
LVDS output receiver D.
LVDS output receiver D.
LVDS input center tap (RX A) (use 0.01 μF to GND).
LVDS input center tap (RX B) (use 0.01 μF to GND).
LVDS input center tap (RX C) (use 0.01 μF to GND).
LVDS input center tap (RX D) (use 0.01 μF to GND).
LVDS reference voltage: 1.0 V ± 3%.
LVDS reference voltage: 1.4 V ± 3%.
Resistor input (use 100
± 1% to RESLO input).
Resistor input.
Reference resistor for PLL (10 k
to ground).
PLL analog V
DD
(3.3 V
±
5%).
PLL analog V
SS
(GND).
O
O
O
O
O
O
O
O
—
—
—
—
I
I
—
—
—
—
—
ref10
ref14
reshi
reslo
rext
pll_V
DD
A
pll_V
SS
A
HSI Test Signals
tstmode
bypass
I
I
Enables CDR test mode. Internal pull-down.
Enables bypassing of the 622 MHz clock synthesis with TSTCLK. Internal
pull-down.
Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-
down.
Test mode reset. Internal pull-down.
Resets receiver clock division counter. Internal pull-up.
Resets transmitter clock division counter. Internal pull-up.
tstclk
I
mreset
resetrn
resettn
I
I
I
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