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| 型號： | ORCAORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 65/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
65
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information
(continued)
In
Table 41, an input refers to a signal flowing into the FGPA logic (out of the embedded core) and an output refers
to a signal flowing out of the FPGA logic (into the embedded core).
Table 41. Embedded Core/FPGA Interface Signal Description
Pin Name
I/O
Description
data_txa<7:0>
data_txa_par
data_txb<7:0>
data_txb_par
data_txc<7:0>
data_txc_par
data_txd<7:0>
data_txd_par
data_rxa<7:0>
data_rxa_par
data_rxa_spe
data_rxa_c1j1
data_rxa_en
data_rxb<7:0>
data_rxb_par
data_rxb_spe
data_rxb_c1j1
data_rxb_en
data_rxc<7:0>
data_rxc_par
data_rxc_spe
data_rxc_c1j1
data_rxc_en
data_rxd<7:0>
data_rxd_par
data_rxd_spe
data_rxd_c1j1
data_rxd_en
toh_clk
toh_txa
toh_txb
toh_txc
toh_txd
tx_toh_ck_en
toh_rxa
toh_rxb
toh_rxc
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
Parallel bus of transmitter A. MSB is bit 7.
Parity for transmitter A.
Parallel bus of transmitter B. MSB is bit 7.
Parity for transmitter B.
Parallel bus of transmitter C. MSB is bit 7.
Parity for transmitter C.
Parallel bus of transmitter D. MSB is bit 7.
Parity for transmitter D.
Parallel bus of receiver A. MSB is bit 7.
Parity for parallel bus of receiver A.
SPE signal for parallel bus of receiver A.
C1J1 signal for parallel bus of receiver A.
Enable for parallel bus of receiver A.
Parallel bus of receiver B. MSB is bit 7.
Parity for parallel bus of receiver B.
SPE signal for parallel bus of receiver B.
C1J1 signal for parallel bus of receiver B.
Enable for parallel bus of receiver B.
Parallel bus of receiver C. MSB is bit 7.
Parity for parallel bus of receiver C.
SPE signal for parallel bus of receiver C.
C1J1 signal for parallel bus of receiver C.
Enable for parallel bus of receiver C.
Parallel bus of receiver D. MSB is bit 7.
Parity for parallel bus of receiver D.
SPE signal for parallel bus of receiver D.
C1J1 signal for parallel bus of receiver D.
Enable for parallel bus of receiver D.
TX and RX TOH serial links clock (25 MHz to 77.76 MHz).
TOH serial link for transmitter A.
TOH serial link for transmitter B.
TOH serial link for transmitter C.
TOH serial link for transmitter D.
TX TOH serial link clock enable.
TOH serial link for receiver A.
TOH serial link for receiver B.
TOH serial link for receiver C.
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