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| 型號(hào)： | OR3T55-4PS240I |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
| 封裝： | SQFP-240 |
| 文件頁(yè)數(shù)： | 153/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T55-4PS240I |
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Lucent Technologies Inc.
47
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Clock Distribution Network
The Series 3 FPGAs provide three types of high-
speed, low-skew clock distributions: system clock, fast
middle clock (Fast Clock), and ExpressCLK. Because
of the great variety of sources and distribution for clock
signals in the
ORCA Series 3, the clock mechanisms
will be described here from the inside out. The clock
connections to the PFU will be described, followed by
clock distribution to the PLC array, clock sources to the
PLC array, and finally ending with clock sources and
distribution in the PICs. The ExpressCLK inputs are
new, dedicated clock inputs in Series 3 FPGAs. They
are mentioned in several of the clock network descrip-
tions and are described fully later in this section.
PFU Clock Sources
Within a PLC there are five sources for the clock signal
of the latches/FFs in the PFU. Two of the signals are
generated off of the long lines (xL) within the PLC: one
from the set of vertical long lines and one from the set
of horizontal long lines. For each of these signals, any
one of the ten long lines of each set, vertical or horizon-
tal, can generate the clock signal. Two of the five PFU
clock sources come from neighboring PLCs. One clock
is generated from the PLC to the left or right of the cur-
rent PLC, and one is generated from the PLC above or
below the current PLC. The selection decision as to
where these signals come from, above/below and left/
right, is based on the position of the PLC in the array
and has to do with the alternating nature of the source
of the system clock spines (discussed later). The last of
the five clock sources is also generated within the PLC.
The E1 control signal, described in the PLC Routing
Resources section, can drive the PFU clock. The E1
signal can come from any xBID routing resource in the
PLC. The selection and switching of clock signals in a
PLC is performed in the FINS. Figure 31 shows the
PFU clock sources for a set of four adjacent PLCs.
Global Control Signals
The four clock signals in each PLC that are generated
from the long lines (xL) in the current PLC or an adja-
cent PLC can also be used to drive the PFU clock
enable (CE), local set/reset (LSR) and add/subtract/
write enable (ASWE) signals. The clock signals gener-
ated from vertical long lines can drive CE and ASWE,
and the clocks generated from horizontal long lines can
drive LSR. This allows for low-skew global distribution
of two of these three control signals with the clock rout-
ing while still allowing a global clock route to occur.
Figure 31. PFU Clock Sources
PFU
PLC
PFU
PLC
PFU
PLC
PFU
PLC
E1
hxL[9:0]
vxL[9:0]
5-6054(F)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T55-4PS240 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
| OR3T80-4PS240I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP240 |
| OR3T80-4PS240 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP240 |
| OR3C80-4B432 | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| OR3C80-4B600 | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T55-5BA256 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA256I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA352 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA352I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5PS208 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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