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| 型號(hào)： | OR3T55-4PS240I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
| 封裝： | SQFP-240 |
| 文件頁(yè)數(shù)： | 131/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T55-4PS240I |
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Lucent Technologies Inc.
27
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Programmable Logic Cells (continued)
BIDI Routing and SLIC Connectivity
The SLIC is connected to the rest of the PLC by the
bidirectional (BIDI) routing segments and the PFU out-
put switching segments coming from the PFU output
multiplexer. The BIDI routing segments (xBID) are
labeled as BL for BIDI-left and BR for BIDI-right. Each
set of BR and BL xBID segments is composed of ten
bidirectional lines (note that these lines are diagramed
as ten input lines to the SLIC and ten output lines from
the SLIC that can be used in a mutually exclusive fash-
ion). Because the SLIC is connected directly to the out-
puts of the PFU, it provides great flexibility in routing
via the xBID segments. The PFU routing segments,
O[9:0], only connect to their respective line in the SLL,
SUL, SUR, and SLR switching segment groups. That
is, O9 only connects to SLL9, SUL9, SUR9, and SLR9.
The BIDI lines provide the capability to connect to the
other member of the routing set. That means, for
example, that O9 can be routed to BR8 or BL8. This
connectivity can be used as a means to distribute or
gather signals on intra-PLC routing without disturbing
inter-PLC resources. As described in the Switching
Routing Segments subsection, the BIDI routing seg-
ments are also used for routes to a diagonally adjacent
PFU.
In addition to the intra-PLC connections, the xBID and
output switching segments also have connectivity to
the x1, x5, and xL inter-PLC routing resources, provid-
ing an alternate routing path rather than using PLC
xSW segments. These connections also provide a path
to the 3-state buffers in the SLIC without encumbering
the xSW segments. In this manner, buffering or 3-state
control can be added to inter-PLC routing without dis-
turbing local functionality within a PFU.
Control Signal and Fast-Carry Routing
PFU control signal and the fast-carry routing are per-
formed using the FINS structure and several dedicated
routing paths. The fast-carry (FC) routing resources
consist of a dedicated bidirectional segment between
each orthogonal pair of PLCs. This means that a fast-
carry can go to or come from each PLC to the right or
left, above or below the subject PLC. The FINS struc-
ture is used to control the switching of these fast-carry
paths between the fast-carry input (FCIN) and fast-
carry output (FCOUT) ports of the PFU.
The PFU control inputs (CE, SEL, LSR, ASWE) and
CIN can be reached via the FINS by two special routing
segments, E1 and E2. The E1 routing segment pro-
vides connectivity between all of the xBID routing seg-
ments and the FINS. It is unidirectional from the BIDI
routing to the FINS. E1 also provides connectivity to
the PFU clock input via FINS for a local clock signal.
The E2 segment connects the SLIC DEC output to the
FINS
and to a group of CIPS that provide bidirectional
connectivity with all of the BIDI routing segments. This
allows the DEC signal to be used in the PFU and/or
routed on the BIDI segments. It also allows signals to
be routed to the PFU on the xBID segments if the SLIC
DEC output is not used.
There is also a dedicated routing segment from the
FINS
to the SLIC TRI input used for BIDI buffer 3-state
control.
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PDF描述 |
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| OR3T55-4PS240 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
| OR3T80-4PS240I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP240 |
| OR3T80-4PS240 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP240 |
| OR3C80-4B432 | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| OR3C80-4B600 | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
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