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參數(shù)資料
| 型號： | OR3T1256PS208I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁數(shù)： | 172/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T1256PS208I-DB |
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70
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
The
ORCA programmable clock manager (PCM) is a
special function block that is used to modify or condi-
tion clock signals for optimum system performance.
Some of the functions that can be performed with the
PCM
are clock skew reduction (both internal and board
level), duty-cycle adjustment, clock delay reduction,
clock phase adjustment, and clock frequency multipli-
cation/division. Due to the different capabilities
required by customer application, each PCM contains
both a PLL (phase-locked loop) and a DLL (delayed-
locked loop) mode. By using PLC logic resources in
conjunction with the PCM, many other functions, such
as frequency synthesis, are possible.
There are two PCMs on each Series 3 device, one in
the lower left corner and one in the upper right corner.
Each can drive two different, but interrelated clock net-
works inside the FPGA. Each PCM can take a clock
input from the ExpressCLK pad in its corner or from
general routing resources. There are also two input
sources that provide feedback to the PCM from the
PLC array. One of these is a dedicated corner Express-
CLK
feedback, and the other is from general routing.
Each PCM sources two clock outputs, one to the cor-
ner ExpressCLK that feeds the CLKCNTRL blocks on
the two sides adjacent to the PCM, and one to the sys-
tem clock spine network through general routing. Fig-
ure 45 shows a high-level block diagram of the PCM.
Functionality of the PCM is programmed during opera-
tion through a read/write interface internal to the FPGA
array or via the conguration bit stream. The internal
FPGA interface comprises write enable and read
enable signals, a 3-bit address bus, an 8-bit input (to
the PCM) data bus, and an 8-bit output data bus. There
is also a PCM output signal, LOCK, that indicates a sta-
ble output clock state. These signals are used to pro-
gram a series of registers to congure the PCM
functional core for the desired functionality.
Operation of the PCM is divided into two modes, delay-
locked loop (DLL) and phase-locked loop (PLL). Some
operations can be performed by either mode and some
are specic to a particular mode. These will be
described in each individual mode section. In general,
DLL mode is preferable to PLL mode for the same
function because it is less sensitive to input clock
noise.
In the discussions that follow, the duty cycle is the per-
cent of the clock period during which the output clock is
high.
5-5828(F)
Figure 45. PCM Block Diagram
USER CONTROL SIGNALS
PCM-FPGA
INTERFACE
PCM CORE
FUNCTIONS
CORNER EXPRESSCLK IN
GENERAL CLOCKIN
FEEDBACK
ExpressCLK
FEEDBACK CLOCK
FROM ROUTING
EXPRESSCLK OUT
SYSTEM CLOCK OUT
(FROM GENERAL ROUTING)
(TO GENERAL ROUTING)
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-6PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256PS240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256PS240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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