參數(shù)資料
型號(hào)： OR3T1256PS208I-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 784 CLBS, 186000 GATES, PQFP208
封裝： PLASTIC, SQFP2-208
文件頁(yè)數(shù)： 132/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3T1256PS208I-DB
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34
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
The programmable input/output cells (PICs) are
located along the perimeter of the device. The PIC’s
name is represented by a two-letter designation to indi-
cate on which side of the device it is located followed
by a number to indicate in which row or column it is
located. The rst letter, P, designates that the cell is a
PIC and not a PLC. The second letter indicates the side
of the array where the PIC is located. The four sides
are left (L), right (R), top (T), and bottom (B). The indi-
vidual I/O pad is indicated by a single letter (either A, B,
C, or D) placed at the end of the PIC name. As an
example, PL10A indicates a pad located on the left
side of the array in the tenth row.
Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os (PIOs) and signicant
routing resources. Each PIO contains input buffers,
output buffers, routing resources, latches/FFs, and
logic and can be congured as an input, output, or
bidirectional I/O.
PICs in the Series 3 FPGAs have signicant local rout-
ing resources, similar to routing in the PLCs. This new
routing increases the ability to x user pinouts prior to
placement and routing of a design and still maintain
routability. The exibility provided by the routing also
provides for increased signal speed due to a greater
variety of signal paths possible.
Included in the PIC routing is a fast path from the input
pins to the SLICs in each of the three adjacent PLCs
(one orthogonal and two diagonal). This feature allows
for input signals to be very quickly processed by the
SLIC decoder function and used on-chip or sent back
off of the FPGA. Also new to the Series 3 PIOs are
latches and FFs and options for using fast, dedicated
clocks called ExpressCLKs. These features will all be
discussed in subsequent sections.
A diagram of a single PIO (one of four in a PIC) is
shown in Figure 22. Table 9 provides an overview of
the programmable functions in an I/O cell.
5-5805(F).c
Figure 22
. OR3C/Txxx Programmable Input/Output (PIO) Image from ispLEVER
IN2
IN1
D0
D1
CK
SP
SD
LSR
INREGMODE
LATCHFF
LATCH
FF
D
CK
NORMAL
INVERTED
RESET
SET
LEVEL MODE
TTL
CMOS
UP
DOWN
NONE
PULL-MODE
BUFFER
TS
FAST
SLEW
SINK
RESET
SET
LSR
SP
CK
D
OUT1
OUT2
ECLK
SCLK
CE
CE_OVER_LSR
LSR_OVER_CE
ASYNC
LSR
ENABLE_GSR
DISABLE_GSR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
NOR
XOR
XNOR
AND
NAND
OR
PIO LOGIC
CLKIN
0
1
0
PAD
Q
1
PD
TO
ROUTING
Q
1
ECLK
SCLK
PMUX
FROM
ROUTING
MODE
LSR
CK
D0 Q
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料
PDF描述
OR3T1256PS240-DB FPGA, 784 CLBS, 186000 GATES, PQFP240
OR3T1256PS240I-DB FPGA, 784 CLBS, 186000 GATES, PQFP240
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