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| 型號(hào)： | OR3T125-4PS208I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 205/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-4PS208I |
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Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
94
Lucent Technologies Inc.
FPGA Configuration Modes (continued)
Daisy-Chaining
Multiple FPGAs can be configured by using a daisy-
chain of the FPGAs. Daisy-chaining uses a lead FPGA
and one or more FPGAs configured in slave serial
mode. The lead FPGA can be configured in any mode
except slave parallel mode. (Daisy-chaining is avail-
able with the boundary-scan ram_w instruction dis-
cussed later.)
All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on positive CCLK and out on negative CCLK
edges.
An upstream FPGA that has received the preamble
and length count outputs a high on DOUT until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bit
pairs. After loading and retransmitting the preamble
and length count to a daisy-chain of slave devices, the
lead device loads its configuration data frames.
The loading of configuration data continues after the
lead device has received its configuration data if its
internal frame bit counter has not reached the length
count. When the configuration RAM is full and the num-
ber of bits received is less than the length count field,
the FPGA shifts any additional data out on DOUT.
The configuration data is read into DIN of slave devices
on the positive edge of CCLK, and shifted out DOUT
on the negative edge of CCLK. Figure 63 shows the
connections for loading multiple FPGAs in a daisy-
chain configuration.
The generation of CCLK for the daisy-chained devices
that are in slave serial mode differs depending on the
configuration mode of the lead device. A master paral-
lel mode device uses its internal timing generator to
produce an internal CCLK at eight times its memory
address rate (RCLK). The asynchronous peripheral
mode device outputs eight CCLKs for each write cycle.
If the lead device is configured in slave mode, CCLK
must be routed to the lead device and to all of the
daisy-chained devices.
5-4488(F)
Figure 63. Daisy-Chain Configuration Schematic
As seen in Figure 63, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
VDD
EPROM
PROGRAM
D[7:0]
OE
CE
A[17:0]
D[7:0]
DONE
M2
M1
M0
DONE
HDC
LDC
RCLK
CCLK
DOUT
DIN
DOUT
DIN
CCLK
DONE
DOUT
INIT
CCLK
VDD
VDD OR
GND
PRGM
M2
M1
M0
PRGM
M2
M1
M0
VDD
HDC
LDC
RCLK
HDC
LDC
RCLK
VDD
ORCA
SERIES
FPGA
SLAVE #2
ORCA
SERIES
FPGA
MASTER
ORCA
SERIES
FPGA
SLAVE #1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4PS208 | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP208 |
| OR3T55-4PS208I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP208 |
| OR3T55-4PS208 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP208 |
| OR3T80-4PS208I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
| OR3T80-4PS208 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| OR3T125-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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