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| 型號(hào)： | OR3T125-4PS208I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 198/210頁(yè) |
| 文件大小： | 2138K |
| 代理商： | OR3T125-4PS208I |
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88
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
FPGA Configuration Modes
There are eight methods for configuring the FPGA.
Seven of the configuration modes are selected on the
M0, M1, and M2 inputs. The eighth configuration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some configuration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
There are three basic FPGA configuration modes:
master, slave, and peripheral. The configuration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input.
In the three peripheral modes, the FPGA acts as a
microprocessor peripheral. Table 33 lists the functions
of the configuration mode pins. Note that two configu-
ration modes previously available on the OR2Cxx and
OR2C/TxxA devices (master parallel down and syn-
chronous peripheral) have been removed for Series 3
devices.
* Motorola is a registered trademark of Motorola, Inc.
Master Parallel Mode
The master parallel configuration mode is generally
used to interface to industry-standard, byte-wide mem-
ory, such as the 2764 and larger EPROMs. Figure 54
provides the connections for master parallel mode. The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads 1 byte of configuration data on the rising
edge of RCLK. The parallel bytes are internally serial-
ized starting with the least significant bit, D0.
Figure 54. Master Parallel Configuration Schematic
In master parallel mode, the starting memory address
is 00000 Hex, and the FPGA increments the address
for each byte loaded.
One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy-chain. The configuration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
Table 33. Configuration Modes
M2
M1
M0
CCLK
Configuration
Mode
Data
0
Output
Master Serial
Serial
0
1
Input
Slave Parallel
Parallel
0
1
0
Output
Microprocessor:
Motorola* Pow-
erPC
Parallel
0
1
Output
Microprocessor:
Intel i960
Parallel
1
0
Output
Master Parallel
Parallel
1
0
1
Output
Async Peripheral
Parallel
110
Reserved
1
Input
Slave Serial
Serial
EPROM
A[17:0]
DONE
M2
M1
M0
HDC
ORCA
SERIES
FPGA
RCLK
LDC
VDD
D[7:0]
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
VDD OR GND
PRGM
PROGRAM
A[17:0]
D[7:0]
OE
CE
5-4483(F)
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| OR3T125-4PS208 | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP208 |
| OR3T55-4PS208I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP208 |
| OR3T55-4PS208 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP208 |
| OR3T80-4PS208I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
| OR3T80-4PS208 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
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參數(shù)描述 |
|---|---|
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