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參數(shù)資料
| 型號： | OR3T125-4BA352I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 143/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-4BA352I |
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38
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Programmable Input/Output Cells
(continued)
Outputs
The PIC’s output drivers have programmable drive
capability and slew rates. Three propagation delays
(fast, slewlim, sinklim) are available on output drivers.
The sinklim mode has the longest propagation delay
and is used to minimize system noise and minimize
power consumption. The fast and slewlim modes allow
critical timing to be met.
The drive current is 12 mA sink/6 mA source for the
slewlim and fast output speed selections and
6 mA sink/3 mA source for the sinklim output. Two
adjacent outputs can be interconnected to increase the
output sink/source current to 24 mA/12 mA.
All outputs that are not speed critical should be config-
ured as sinklim to minimize power and noise. The num-
ber of outputs that switch simultaneously in the same
direction should be limited to minimize ground bounce.
To minimize ground bounce problems, locate heavily
loaded output buffers near the ground pads. Ground
bounce is generally a function of the driving circuits,
traces on the printed-circuit board, and loads and is
best determined with a circuit simulation.
At powerup, the output drivers are in slewlim mode,
and the input buffers are configured as TTL-level com-
patible (CMOS for OR3Txxx) with a pull-up. If an output
is not to be driven in the selected configuration mode, it
is 3-stated.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. Additionally, there is a fast,
open-drain output option that directly connects the out-
put signal to the 3-state control, allowing the output
buffer to either drive to a logic 0 or 3-state, but never to
drive to a logic 1. Because there is no explicit route
required to create the open-drain output, its response
is very fast. Like the input side of the PIO, there are two
output connections from PIC routing to the output side
of the PIO, OUT1 and OUT2. These connections pro-
vide for flexible routing and can be used in data manip-
ulation in the PIO as described in subsequent
paragraphs.
An FF has been added to the output path of the PIO.
The register has a local set/reset and clock enable.
The LSR has the option to be synchronous or asyn-
chronous and have priority set as clock enable over
LSR or LSR over clock enable. Clocking to the output
FF can come from either the system clock or the
ExpressCLK
associated with the PIC. The input to the
FF can come from either OUT1 or OUT2, or it can be
tied to VDD or GND. Additionally, the input to the FF
can be inverted.
Output Multiplexing
The Series 3 PIO output FF can be combined with the
new PIO logic block to perform output data multiplexing
with no PLC resources required. The PIO logic block
has three multiplexing modes: OUT1OUTREG,
OUT2OUTREG, and OUT1OUT2. OUT1OUTREG and
OUT2OUTREG are equivalent except that either OUT1
or OUT2 is MUXed with the FF, where the FF data is
output on the clock phase after the active edge. The
simplest multiplexing mode is OUT1OUT2. In this
mode, the signal at OUT1 is output to the pad while the
clock is low, and the signal on OUT2 is output to the
pad when the clock is high. Figure 25 shows a simple
schematic of a PIO in OUT1OUT2 mode and a general
timing diagram for multiplexing an address and data
signal.
Often an address will be used to generate or read a
data sample from memory with the goal of multiplexing
the data onto a single line. In this case, the address
often precedes the data by one clock cycle.
OUT1OUTREG and OUT2OUTREG modes of the PIO
logic can be used to address this situation.
Because OUT1OUTREG mode is equivalent to
OUT2OUTREG, only OUT2OUTREG mode is
described here. Figure 26 shows a simple PIO sche-
matic in OUT2OUTREG mode and general timing for
multiplexing data with a leading address. The address
signal on OUT1 is registered in the PIO FF. This delays
the address so that it aligns with the data signal. The
PIO logic block then sends the OUTREG signal
(address) to the pad when the clock is high and the
OUT2 signal (data) to the pad when the clock is low,
resulting in an aligned, multiplexed signal.
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PDF描述 |
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| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-5B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-5B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-6B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-6B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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