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| 型號(hào)： | OR3T125-4BA352I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 136/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-4BA352I |
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Lucent Technologies Inc.
31
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Programmable Logic Cells (continued)
PLC Architectural Description
Figure 21 is an architectural drawing of the PLC (as
seen in
ORCA Foundry) that reflects the PFU, the rout-
ing segments, and the CIPs. A discussion of each of
the letters in the drawing follows.
A. These are switching routing segments (xSW) that
give the router flexibility. In general switching theory,
the more levels of indirection there are in the routing,
the more routable the network is. The xSW seg-
ments can also connect to the xSW lines in adjacent
PLCs.
B. These CIPs connect the x1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal x1
segment from the right or the right end of the hori-
zontal x1 segment from the left, or both. By symme-
try, the same principle is used in the vertical
direction.
C. This set of CIPs is used to connect the x1 and x5
nets to the xSW segments or to other x1 and x5
nets. The CIPs on the major diagonal allow data to
be transmitted on a bit-by-bit basis from x1 nets to
the xSW segments and between the x1 and x5 nets.
D. This structure is the supplemental logic and inter-
connect cell, or SLIC. It contains 3-statable bidirec-
tional buffers and logic for building decoders and
AND-OR-INVERT type structures.
E. These are the primary and secondary elements of
the flexible input structure or FINS. FINS is a switch
matrix that provides high connectivity while retaining
routing capability. FINS also includes feedback
paths for softwired LUT implementation.
F. This is the PFU output switch matrix. It is a complex
switch network which, like the FINS at the input, pro-
vides high connectivity and maintains routability.
G. This set of CIPs allows a xBID segment to transfer a
signal to/from xSW segments on each side. The
BIDIs can access the PFU through the xSW seg-
ments. These CIPs allow data to be routed through
the BIDIs for amplification or 3-state control and
continue to another PLC. They also provide an alter-
native routing resource to improve routability.
H. These CIPs are used to transfer data from/to the
xBID segments to/from the x1 and xL routing seg-
ments. These CIPs have been optimized to allow
the BIDI buffers to drive the loads usually seen
when using each type of routing segment.
I. Clock input to PFU.
J. These are the ten switched output routing segments
from the PFU. They connect to the PLC switching
segments and are input to the SLIC.
K. These lines deliver the auxiliary signals clock enable
(CE), local set/reset (LSR), front-end select (SEL),
add/subtract/write enable (ASWE), as well as the
carry signals (CIN and FCIN) to the latches/FFs.
L. This is the local clock buffer. Any of the horizontal
and vertical xL lines can drive the clock input of the
PLC latches/FFs. The clock routing segments
(vCLK and hCLK) and multiplexers/drivers are used
to connect to the xL routing segments for low-skew,
low-delay global signals.
M. These routing segments are used to route the fast-
carry signal to/from the neighboring four PLCs. The
carry-out (COUT) and registered carry-out (REG-
COUT) can also be routed out of the PFU.
N. This is the E2 control routing segment. It runs from
the SLIC DEC output to the FINS and also provides
connectivity to all xBID segments.
O. The xH routing segments run one-half the length
(width) of the array before being broken by a CIP.
P. These CIPs connect the xH segments to the xSW
segments.
Q. The xBID segments are used to connect the SLIC to
the xSW segments, x1 segments, x5 segments, and
xL lines, as well as providing for diagonal PLC to
PLC connections.
R. These CIPs provide connections from the xBID seg-
ments to the E1/E2 routing segments that feed PFU
control inputs CE, LSR, CIN, ASWE, SEL, and the
clock input. Alternatively, these CIPs connect the
BIDI lines to the decoder (DEC) output of the SLIC,
for routing the DEC signal.
S. These are clock spines (vCLK and hCLK) with the
multiplexers and drivers to connect to the xL routing
segments.
T. These CIPs connect xBID segments to switching
segments in diagonally and orthogonally adjacent
PFUs.
U. These CIPs connect xSW segments to the PFU out-
put segments.
V. These CIPS connect xSW segments in orthogonally
adjacent PFUs.
W.This is the SLIC 3-state control routing segment
from the FINS to the SLIC 3-state control.
X. This is the E1 control routing segment. It provides a
PFU input path from all xBID segments.
Y. These CIPs are used to select which xBID segments
are connected to the E1/E2 signal as described in
(R).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-5B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-5B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-6B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-6B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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