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| 型號(hào)： | OR3C80-5BC600I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁(yè)數(shù)： | 52/210頁(yè) |
| 文件大小： | 2138K |
| 代理商： | OR3C80-5BC600I |
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Lucent Technologies Inc.
145
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Special-Purpose Pins (continued)
A11/MPI_IRQ
O
I/O
MPI
active-low interrupt request output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A10/MPI_BI
O
I/O
PowerPC mode MPI burst inhibit output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A9/MPI_ACK
O
I/O
In
PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For
i960 MPI operation, it is the active-low ready/record (RDYRCV) output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A8/MPI_RW
I
I/O
In
PowerPC mode MPI operation, this is the active-low write/active-high read control signals.
For
i960 operation, it is the active-high write/active-low read control signal.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A7/MPI_CLK
I
I/O
This is the clock used for the synchronous MPI interface. For
PowerPC, it is the CLKOUT
signal. For
i960, it is the system clock that is chosen for the i960 external bus interface.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A[4:0]
I
I/O
For
PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in
PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note
that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in
i960 MPI mode.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
A[1:0]/
MPI_BE[1:0]
I
I/O
For
i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are used as
address bits A[1:0] in
i960 byte-wide operation.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
D[7:0]
I
I/O
During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive
configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input. D[7:0] are also the data pins for
PowerPC microprocessor mode and the
address/data pins for
i960 microprocessor mode.
After configuration, the pins are user-programmable I/O pins (see Note).
DIN
I
I/O
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
DOUT
O
I/O
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin (see Note).
Pin Information (continued)
Table 68. Pin Descriptions (continued)
Symbol
I/O
Description
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4BC600I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PBGA600 |
| OR3T80-4BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3T80-5BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3T80-6BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C805PS208 | 制造商:ORCA 功能描述:NEW |
| OR3C80-5PS208 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C805PS208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-5PS208I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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