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參數(shù)資料
| 型號： | OR3C80-5BC600I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁數(shù)： | 45/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3C80-5BC600I |
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Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Lucent Technologies Inc.
139
Estimating Power Dissipation
OR3Cxx
The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
PT =
Σ PPLC + Σ PPIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-
out of two:
PPFU = 0.136 mW/MHz
For each PFU output that switches, 0.136 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power
dissipated in each PFU that uses this particular clock,
and the power from the subset of those PFUs that are
configured as synchronous memory. Therefore, the
clock power can be calculated for the four parts using
the following equations:
OR3C55 Clock Power
P
= [0.183 mW/MHz
+ (0.235 mW/MHz/Branch) (# Branches)
+ (0.033 mW/MHz/PFU) (# PFUs)
+ (0.008 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3C55 clock power
≈ 14.64 mW/MHz.
OR3C80 Clock Power
P
= [0.224 mW/MHz
+ (0.288 mW/MHz/Branch) (# Branches)
+ (0.033 mW/MHz/PFU) (# PFUs)
+ (0.008 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3C80 clock power
≈ 21.06 mW/MHz.
The power dissipated in a PIC is the sum of the power
dissipated in the four PIOs in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each PIO depends on
whether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
The power dissipated by a TTL input buffer is esti-
mated as:
PTTL = 2.2 mW + 0.17 mW/MHz
The power dissipated by an input buffer is estimated
as:
PCMOS = 0.17 mW/MHz
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
POUT = (CL + 8.8 pF) x VDD2 x F Watts
where the unit for CL is farads, and the unit for F is Hz.
As an example of estimating power dissipation, sup-
pose that a fully utilized OR3C55 has an average of
six outputs for each of the 324 PFUs, that 10 clock
branches are used so that the clock is driven to the
entire PLC array, that 150 of the 324 PFUs have FFs
clocked at 40 MHz, and that the PFU outputs have an
average activity factor of 20%.
Twenty TTL-configured inputs, 20 CMOS-configured
inputs, 32 outputs driving 30 pF loads, and 16 bidirec-
tional I/Os driving 50 pF loads are also generated from
the 40 MHz clock with an average activity factor of
20%. All of the output PIOs are registered, and 30 of
the input PIOs are registered. The worst-case (VDD =
5.25 V) power dissipation is estimated as follows:
PPFU
= 324 x 6 (0.136 mW/MHz x 20 MHz x 20%)
= 1057.54 mW
PCLK
= [0.183 mW/MHz + (0.235 mW/MHz – Branch)
(10 Branches)
+ (0.033 mW/MHz – PFU) (150 PFUs)
+ (0.008 mW/MHz/PIO (58 PIOs)]
= 318.63 mW
PTTL
= 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz x 20%)]
= 57.6 mW
PCMOS = 20 x [0.17 mW x 20 MHz x 20%]
= 13.6 mW
POUT
= 32 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
=136.89 mW
PBID
= 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
= 103.72 mW
Total
= 1.69 W
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