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參數(shù)資料
| 型號(hào)： | OR3C80-4B432 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁(yè)數(shù)： | 147/210頁(yè) |
| 文件大小： | 2138K |
| 代理商： | OR3C80-4B432 |
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Lucent Technologies Inc.
41
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Programmable Input/Output Cells
(continued)
PIC Routing Resources
The PIC routing borrows many of the concepts and
constructs from the PLC routing. It is designed to be
able to gather an 8-bit bidirectional bus from any eight
consecutive I/O pads and route them to either or both
of the two adjacent PLCs. The eight I/O bits do not
need to start at a PIC boundary; that is, they may start
at one of the middle two PIOs in a PIC and span three
PICs.
Substantial routing has been added to the PIC to off-
load PLC routing from being used to move signals
around the PLC array perimeter. This saves PLC rout-
ing for logic purposes and provides greater flexibility for
locking design pinouts prior to final placement and rout-
ing of the device, or allowing a change in the pinout
late in the design cycle. The PIC routing has also been
increased substantially to allow routing to the complex
PIO cells that now allow multiple inputs and outputs per
device pin, along with new sequential control signals,
such as clock enable, LSR, and clock.
PICs are grouped in pairs for purposes of discussing
PIC routing. On the sides of a device, the PICs in a pair
are referred to as top and bottom. On the top or bottom
of a device, the PICs in a pair are referred to as left or
right. For example, on the top edge of the device, the
leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2
is the right PIC of that pair. The next PIC to the right,
PT3, is the left PIC of the next pair, and so on.
The need for PIC pairs stems from the routing of
switching segments and PLC half- and long-line driv-
ers. As described below, the connectivity for these
types of routing is grouped across pairs of PICs to pro-
vide complete and fast routing of I/O signals between a
given PIC and the three adjacent PLCs: one orthogonal
and two diagonal.
PIC routing segments use the same terminology as
PLC routing segments, but are prefixed with a p to dis-
tinguish them as belonging to the PICs.
PIC Switching Segments. Each PIC has two groups
of switching segments (pSW), each group having eight
lines with connectivity to the PIOs in groups of four.
One set of switching segments connects to the PIC to
the left (above), and the other set connects to the
switching segments of the PIC to the right (below). This
means of connectivity between PICs using staggered
connections of groups of switching segments allows a
given PIC to route signals to both adjacent PICs and all
adjacent PLCs efficiently. This provides single signal
routing flexibility and routing of multiple buses on
groups of I/Os without tying up global routing
resources.
px1 Routing Segments. There are five px1 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides, each broken by a
CIP in each PIC. The px1 segments have connectivity
to the pSW segments and to the x1 routing segments
of the two adjacent PLCs.
px2 Routing Segments. There are five px2 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. To provide greater
routing flexibility, the CIPs that break the px2 segments
every two PICs are staggered across the two PICs in a
pair. One PIC of the pair has break CIPs on the even
numbered px2 segments, and the other has them on
the odd numbered px2 segments. The px2 segments
have connectivity to the pSW segments and to the x1
routing segments of the two adjacent PLCs.
px5 Routing Segments. There are ten px5 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. Two of the ten seg-
ments are broken in each PIC so that each segment is
broken every five PICs. All ten px5 segments break at
the corners of the chip, allowing independent px5 rout-
ing on each edge of the chip. The px5 routing seg-
ments connect to the pSW segments and the x5 and
xH routing segments of the two adjacent PLCs.
pxH Routing Segments. Each PIC contains eight pxH
routing segments that run parallel to the edge of the
chip on which the PIC resides. The pxH segments
have connectivity with the xL, xH, and one set of xBID
routing segments in the immediately adjacent PLC.
pxL Routing Segments. There are ten pxL routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. Each of the xL lines
makes a connection to an xL line from the adjacent
PLC. PIC long lines (xL) can be used for global signal
distribution just as PLC xL lines can.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| OR3C80-4BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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