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| 型號(hào)： | OR3C55 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | OR3C55 |
Lucent Technologies Inc.
3
Preliminary Product Brief
April 1999
ORCA Series 3 FPGAs
Support
I
ORCAFoundry Development System support.
I
Supported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
Description
FPGA Overview
The ORCASeries 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA (Series 2) from Lucent Technologies
Microelectronics Group, with enhancements and inno-
vations geared toward today’s high-speed designs and
tomorrow’s systems on a single chip. Designed from
the start to be synthesis friendly and to reduce place
and route times while maintaining the complete
routability of the ORCA Series 2 devices, the Series 3
family more than doubles the logic available in each
logic block and incorporates system-level features that
can further reduce logic requirements and increase
system speed. ORCA Series 3 devices contain many
new patented enhancements and are offered in a vari-
ety of packages, speed grades, and temperature
ranges.
The ORCASeries 3 FPGAs consist of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU (see Figure 1), but
decoders, PAL-like functions, and 3-state buffering can
be performed in the SLIC (see Figure 2). The PICs pro-
vide device inputs and outputs and can be used to reg-
ister signals and to perform input demultiplexing, output
multiplexing, and other functions on two output signals
(see Figure 3). Some of the system-level functions
include the new microprocessor interface (MPI) and the
programmable clock manager (PCM).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4
single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT to
perform PAL-like functions. The 3-state drivers in the
SLIC and their direct connections to the PFU outputs
make fast, true 3-state buses possible within the FPGA,
reducing required routing and allowing for real-world
system performance.
PIC Logic
The OR3C/Txxx PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
ORCA Series 2 buffer with a new, fast, open-drain
option for ease of use on system buses. The output
buffer signal can be inverted, and the 3-state control
can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
tered or nonregistered.
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| OR3C55-4BA256 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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