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參數(shù)資料
| 型號： | OR3C55 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 232K |
| 代理商： | OR3C55 |
Preliminary Product Brief
ORCA Series 3 FPGAs
April 1999
6
Lucent Technologies Inc.
Description
(continued)
System Features
The Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface (MPI)
and its innovative programmable clock manager
(PCM). These functional blocks allow for easy glueless
system interfacing and the capability to adjust to vary-
ing conditions in today’s high-speed systems.
The MPI provides a glueless interface between the
FPGA and PowerPCand i960microprocessors. It can
be used for configuration and readback, as well as for
monitoring FPGA status. The MPI also provides a gen-
eral-purpose microprocessor interface to the FPGA
user-defined logic following configuration.
Two PCMs are provided on each Series 3 device. Each
PCM can be used to manipulate the frequency, phase,
and duty cycle of a clock signal. Clocks may be input
from the dedicated corner ExpressCLK input (in the
same corner as the PCM block) or from general rout-
ing. Output clocks from the PCM can be sent to the
system clock spines and/or to the ExpressCLK and fast
clock spines on the edges of the device adjacent to the
PCM. ExpressCLK/fast clock and system clock output
frequencies can differ by up to a factor of 8 to allow
slow I/O clocking with fast internal processing (or vice
versa). Each PCM is capable of manipulating clocks
from 5 MHz to 120 MHz. Frequencies can be adjusted
from 1/8x to 64x the input clock frequency, and duty
cycles and phase delays can be adjusted from 3.125%
to 96.875%.
Routing
The abundant routing resources of the Series 3 FPGAs
are organized to route signals individually or as buses
with related control signals. Clocks are routed on a low-
skew, high-speed distribution network and may be
sourced from PLC logic, externally from any I/O pad, or
from the very fast ExpressCLK pins. ExpressCLKs may
be glitchlessly and independently enabled and disabled
with a programmable control signal using the new
StopCLK feature. The improved PIC routing resources
are now similar to the patented intra-PLC routing
resources and provide great flexibility in moving signals
to and from the PIOs. This flexibility translates into an
improved capability to route designs at the required
speeds when the I/O signals have been locked to spe-
cific pins.
Configuration
The FPGA’s functionality is determined by internal con-
figuration RAM. The FPGA’s internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM or any
other storage media. Serial EEPROMs provide a sim-
ple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
5-5805(F).c
Figure 3. Series 3 Programmable Input/Output (PIO) Image from ORCA Foundry
IN2
IN1
D0
D1
CK
SP
SD
LSR
INREGMODE
LATCHFF
LATCH
FF
D
CK
NORMAL
INVERTED
RESET
SET
LEVEL MODE
TTL
CMOS
UP
DOWN
NONE
PULL-MODE
BUFFER
MODE
TS
FAST
SLEW
SINK
RESET
SET
LSR
SP
CK
D
OUT1
OUT2
ECLK
SCLK
CE
CE_OVER_LSR
LSR_OVER_CE
ASYNC
LSR
ENABLE_GSR
DISABLE_GSR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
NOR
XOR
XNOR
AND
NAND
OR
PIO LOGIC
CLKIN
0
0
1
0
PAD
Q
Q
1
PD
T
Q
1
ECLK
SCLK
PMUX
F
LSR
CK
D0 Q
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相關代理商/技術參數(shù) |
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