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參數(shù)資料
| 型號(hào)： | OR3C55 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 232K |
| 代理商： | OR3C55 |
Preliminary Product Brief
ORCA Series 3 FPGAs
April 1999
2
Lucent Technologies Inc.
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCAOR3C/Txxx include:
I
Full PCI local bus compliance.
I
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC
processors with user-configurable
address space provided.
I
Parallel readback of configuration data capability with
the built-in microprocessor interface.
I
Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
I
True, internal, 3-state, bidirectional buses with simple
control provided by the SLIC.
I
32 x 4 RAM per PFU, configurable as single- or dual-
port at >183 MHz (-7 speed). Create large, fast RAM/
ROM blocks (128 x 8 in only eight PFUs) using the
SLIC decoders as bank drivers.
* i960is a registered trademark of Intel Corporation.
PowerPCis a registered trademark of International Business
Machines Corporation.
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Table 2. ORCA OR3C/Txxx System Performance
Parameter
# PFUs
Speed
Unit
-4
76
76
-5
99
99
-6
128
128
-7
161
161
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
36-bit Parity Check (internal)
2
2
MHz
MHz
11.5
8
15
19
50
74
24
65
101
30
79
123
37
99
159
MHz
MHz
MHz
4
4
94
122
122
158
147
195
183
237
MHz
MHz
8
8
86
86
112
112
135
135
168
168
MHz
MHz
0.25
0
4.87
2.35
3.66
1.82
2.58
1.23
2.03
0.99
ns
ns
2
0
2
16.06
6.91
16.06
12.07
5.41
12.07
9.01
4.21
9.01
7.03
3.37
7.03
ns
ns
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| OR3C55-4BA256 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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| OR3C55-4BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C55-4BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C55-4PS208 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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