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| 型號： | OR2C40A-3S304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 7/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C40A-3S304 |
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Lucent Technologies Inc.
7
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Logic Cells
(continued)
Table 3 lists the basic operating modes of the LUT. The
operating mode affects the functionality of the PFU
input and output ports and internal PFU routing. For
example, in some operating modes, the WD[3:0] inputs
are direct data inputs to the PFU latches/FFs. In the
dual 16 x 2 memory mode, the same WD[3:0] inputs
are used as a 4-bit data input bus into LUT memory.
The PFU is used in a variety of modes, as illustrated in
Figures 4 through 11, and it is these specific modes
that are most relevant to PFU functionality.
PFU Control Inputs
The four control inputs to the PFU are clock (CK), local
set/reset (LSR), clock enable (CE), and C0. The CK,
CE, and LSR inputs control the operation of all four
latches in the PFU. An active-low global set/reset
(GSRN) signal is also available to the latches/FFs in
every PFU. Their operation is discussed briefly here,
and in more detail in the Latches/Flip-Flops section.
The polarity of the control inputs can be inverted.
The CK input is distributed to each PFU from a vertical
or horizontal net. The CE input inhibits the latches/FFs
from responding to data inputs. The CE input can be
disabled, always enabling the clock. Each latch/FF can
be independently programmed to be set or reset by the
LSR and the global set/reset (GSRN) signals. Each
PFU’s LSR input can be configured as synchronous or
asynchronous. The GSRN signal is always asynchro-
nous. The LSR signal applies to all four latches/FFs in
a PFU. The LSR input can be disabled (the default).
The asynchronous set/reset is dominant over clocked
inputs.
The C0 input is used as an input into the special PFU
gates for wide functions in combinatorial logic mode.
In the memory modes, this input is also used as the
write-port enable input. The C0 input can be disabled
(the default).
Look-Up Table Operating Modes
The look-up table (LUT) can be configured to operate
in one of three general modes:
I
Combinatorial logic mode
I
Ripple mode
I
Memory mode
The combinatorial logic mode uses a 64-bit look-up
table to implement Boolean functions. The two 5-bit
logic inputs, A[4:0] and B[4:0], and the C0 input are
used as LUT inputs. The use of these ports changes
based on the PFU operating mode.
The functionality of the LUT is determined by its operat-
ing mode. The entries in Table 3 show the basic modes
of operation for combinatorial logic, ripple, and memory
functions in the LUT. Depending on the operating
mode, the LUT can be divided into sub-LUTs. The LUT
is comprised of two 32-bit half look-up tables, HLUTA
and HLUTB. Each half look-up table (HLUT) is com-
prised of two quarter look-up tables (QLUTs). HLUTA
consists of QLUT2 and QLUT3, while HLUTB consists
of QLUT0 and QLUT1. The outputs of QLUT0, QLUT1,
QLUT2, and QLUT3 are F0, F1, F2, and F3, respec-
tively.
Table 3. Look-Up Table Operating Modes
For combinatorial logic, the LUT can be used to do any
single function of six inputs, any two functions of five
inputs, or four functions of four inputs (with some inputs
shared), and three special functions based on the two
five-input functions and C0.
Mode
F4A
Function
Two functions of four inputs, some inputs
shared (QLUT2/QLUT3)
Two functions of four inputs, some inputs
shared (QLUT0/QLUT1)
One function of five inputs (HLUTA)
One function of five inputs (HLUTB)
4-bit ripple (LUT)
16 x 2 asynchronous memory (HLUTA)
16 x 2 asynchronous memory (HLUTB)
SSPM 16 x 4 synchronous single-port memory
SDPM 16 x 2 synchronous dual-port memory
F4B
F5A
F5B
R
MA
MB
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| OR2C40A-3T304 | Field-Programmable Gate Arrays |
| OR2C40A-3T304I | Field-Programmable Gate Arrays |
| OR2C40A-3T432 | Field-Programmable Gate Arrays |
| OR2C40A-3T432I | Field-Programmable Gate Arrays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LatticeECP/EC or LatticeXP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS304-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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