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參數(shù)資料
| 型號： | OR2C40A-3S304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 126/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C40A-3S304 |
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Lucent Technologies Inc.
126
Data Sheet
June 1999
ORCA Series 2 FPGAs
Package Thermal Characteristics
There are three thermal parameters that are in com-
mon use:
Θ
JA
,
ψ
JC, and
Θ
JC
. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
The data base containing the thermal values for all of
Lucent Technologies’ IC packages is currently being
updated to conform to modern JEDEC standards.
Thus, Table 29 contains the currently available thermal
specifications for Lucent Technologies’ FPGA pack-
ages mounted on both JEDEC and non-JEDEC test
boards. The thermal values for the newer package
types correspond to those packages mounted on a
JEDEC four-layer board (indicated as Note 2 in the
table). The values for the older packages, however, cor-
respond to those packages mounted on a non-JEDEC,
single-layer, sparse copper board (see Note 1). It
should also be noted that the values for the older pack-
ages are considered conservative.
Θ
JA
This is the thermal resistance from junction to ambient
(a.k.a. theta-JA, R-theta, etc.).
where T
J
is the junction temperature, T
A
is the ambient
air temperature, and Q is the chip power.
Experimentally,
Θ
JA
is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (T
J
) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (T
A
) is noted. Note that
Θ
JA
is
expressed in units of °C/watt.
ψ
JC
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by:
where T
C
is the case temperature at top dead center,
T
J
is the junction temperature, and Q is the chip power.
During the
Θ
JA
measurements described above,
besides the other parameters measured, an additional
temperature reading, T
C
, is made with a thermocouple
attached at top-dead-center of the case.
ψ
JC
is also
expressed in units of °C/watt.
Θ
JC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by:
The parameters in this equation have been defined
above. However, the measurements is performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates
Θ
JC
from
ψ
JC.
Θ
JC
is a true thermal resistance and is
expressed in units of °C/watt.
Θ
JB
This is the thermal resistance from junction to board
(a.k.a.,
Θ
JL)
. It is defined by:
J
T
B
–
Q
where T
B
is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that
Θ
JB
is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
Θ
JA
J
T
T
A
–
Q
=
ψ
JC
J
T
T
C
–
Q
=
Θ
JC
J
T
T
C
–
Q
=
Θ
JB
T
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C40A-3T304 | Field-Programmable Gate Arrays |
| OR2C40A-3T304I | Field-Programmable Gate Arrays |
| OR2C40A-3T432 | Field-Programmable Gate Arrays |
| OR2C40A-3T432I | Field-Programmable Gate Arrays |
| OR2T04A-3T84 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LatticeECP/EC or LatticeXP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS304-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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