- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383706 > OR2C40A-3S304 (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | OR2C40A-3S304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 20/192頁(yè) |
| 文件大小： | 3148K |
| 代理商： | OR2C40A-3S304 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
20
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Logic Cells
(continued)
XL Lines.
The long XL lines run vertically and horizon-
tally the height and width of the array, respectively.
There are a total of eight XL lines per PLC: four hori-
zontal (HXL[3:0]) and four vertical (VXL[3:0]). Each
PLC column has four XL lines, and each PLC row has
four XL lines. Each of the XL lines connects to the two
PICs at either end. The Series 2, which consists of a
18 x 18 array of PLCs, contains 72 VXL and 72 HXL
lines. They are intended primarily for global signals
which must travel long distances and require minimum
delay and/or skew, such as clocks.
There are three methods for routing signals onto the XL
lines. In each PLC, there are two long-line drivers: one
for a horizontal XL line, and one for a vertical XL line.
Using the long-line drivers produces the least delay.
The XL lines can also be driven directly by PFU outputs
using the BIDI lines. In the third method, the XL lines
are accessed by the bidirectional buffers, again using
the BIDI lines.
XH Lines
. Four by half (XH) lines run horizontally and
four XH lines run vertically in each row and column in
the array. These lines travel a distance of one-half the
PLC array before being broken in the middle of the
array, where they connect to the interquad block (dis-
cussed later). They also connect at the periphery of the
FPGA to the PICs, like the XL lines. The XH lines do
not twist like XL lines, allowing nibble-wide buses to be
routed easily.
Two of the three methods of routing signals onto the
XL lines can also be used for the XH lines. A special
XH line driver is not supplied for the XH lines.
Clock Lines.
For a very fast and low-skew clock (or
other global signal tree), clock lines run the entire
height and width of the PLC array. There are two hori-
zontal clock lines per PLC row (CKL, CKR) and two
vertical clock lines per PLC column (CKT, CKB). The
source for these clock lines can be any of the four I/O
buffers in the PIC. The horizontal clock lines in a row
(CKL, CKR) are driven by the left and right PICs,
respectively. The vertical clock lines in a column (CKT,
CKB) are driven by the top and bottom PICs, respec-
tively.
The clock lines are designed to be a clock spine. In
each PLC, there is a fast connection available from the
clock line to the long-line driver (described earlier).
With this connection, one of the clock lines in each PLC
can be used to drive one of the four XL lines perpendic-
ular to it, which, in turn, creates a clock tree.
This feature is discussed in detail in the Clock Distribu-
tion Network section.
Minimizing Routing Delay
The CIP is an active element used to connect two lines.
As an active element, it adds significantly to the resis-
tance and capacitance of a net, thus increasing the
net’s delay. The advantage of the X1 line over a X4 line
is routing flexibility. A net from PLC db to PLC cb is eas-
ily routed by using X1 lines. As more CIPs are added to
a net, the delay increases. To increase speed, routes
that are greater than two PLCs away are routed on the
X4 lines because a CIP is located only in every fourth
PLC. A net that spans eight PLCs requires seven X1
lines and six CIPs. Using X4 lines, the same net uses
two lines and one CIP
All routing resources in the PLC can carry 4-bit buses.
In order for data to be used at a destination PLC that is
in data path mode, the data must arrive unscrambled.
For example, in data path operation, the least signifi-
cant bit 0 must arrive at either A[0] or B[0]. If the bus is
to be routed by using either X4 or XL lines (both of
which twist as they propagate), the bus must be placed
on the appropriate lines at the source PLC so that the
data arrives at the destination unscrambled. The
switching lines provide the most efficient means of con-
necting adjacent PLCs. Signals routed with these lines
have minimum propagation delay.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C40A-3T304 | Field-Programmable Gate Arrays |
| OR2C40A-3T304I | Field-Programmable Gate Arrays |
| OR2C40A-3T432 | Field-Programmable Gate Arrays |
| OR2C40A-3T432I | Field-Programmable Gate Arrays |
| OR2T04A-3T84 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS240-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeECP/EC or LatticeXP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS304-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。