- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383706 > OR2C40A-3S304 (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | OR2C40A-3S304 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 61/192頁 |
| 文件大小： | 3148K |
| 代理商： | OR2C40A-3S304 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
Lucent Technologies Inc.
61
Data Sheet
June 1999
ORCA Series 2 FPGAs
ORCA Timing Characteristics
(continued)
Table 15B. Derating for Commercial/Industrial
Devices (OR2TxxB)
Power Supply Voltage
3.0 V
3.15 V
–40
0.81
0.78
0
0.86
0.83
25
0.9
0.87
85
1.0
0.95
100
1.02
0.98
125
1.06
1.03
Note:
The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed bins
higher than that designated on a product brand. Design
practices need to consider best-case timing parame-
ters (e.g., delays = 0), as well as worst-case timing.
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal inter-
connect in the path. The number of logic elements that
can be driven (or fan-out) by PFUs is unlimited,
although the delay to reach a valid logic level can
exceed timing requirements. It is difficult to make accu-
rate routing delay estimates prior to design compilation
based on fan-out. This is because the CAE software
may delete redundant logic inserted by the designer to
reduce fan-out, and/or it may also automatically reduce
fan-out by net splitting.
The waveform test points are given in the Measure-
ment Conditions section of this data sheet. The timing
parameters given in the electrical characteristics tables
in this data sheet follow industry practices, and the val-
ues they reflect are described below.
I
Propagation Delay
—the time between the specified
reference points. The delays provided are the worst
case of the tphh and tpll delays for noninverting func-
tions, tplh and tphl for inverting functions, and tphz
and tplz for 3-state enable.
I
Setup Time
—the interval immediately preceding the
transition of a clock or latch enable signal, during
which the data must be stable to ensure it is recog-
nized as the intended value.
I
Hold Time
—the interval immediately following the
transition of a clock or latch enable signal, during
which the data must be held stable to ensure it is rec-
ognized as the intended value.
I
3-state Enable
—the time from when a TS[3:0] signal
becomes active and the output pad reaches the high-
impedance state.
Estimating Power Dissipation
OR2CxxA
The total operating power dissipated is estimated by
summing the standby (I
DDSB
), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
P
T
=
Σ
P
PLC
+
Σ
P
PIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
P
PFU
= 0.16 mW/MHz
For each PFU output that switches, 0.16 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dis-
sipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that is config-
ured in either of the two synchronous modes (SSPM or
SDPM). Therefore, the clock power can be calculated
for the four parts using the following equations:
OR2C04A Clock Power
P
= [0.62 mW/MHz
+ (0.22 mW/MHz – Branch) (# Branches)
+ (0.022 mW/MHz – PFU) (# PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2C04A clock power
≈
3.9 mW/MHz.
T
J
(°C)
3.3 V
0.76
0.80
0.83
0.93
0.95
0.98
3.45 V
0.74
0.77
0.8
0.88
0.91
0.95
3.6 V
0.73
0.76
0.78
0.86
0.88
0.92
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C40A-3T304 | Field-Programmable Gate Arrays |
| OR2C40A-3T304I | Field-Programmable Gate Arrays |
| OR2C40A-3T432 | Field-Programmable Gate Arrays |
| OR2C40A-3T432I | Field-Programmable Gate Arrays |
| OR2T04A-3T84 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use LatticeECP/EC or LatticeXP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4PS304-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復。