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參數資料
| 型號： | NT5CB256M4AN-BF |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA78 |
| 封裝： | 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78 |
| 文件頁數： | 24/106頁 |
| 文件大?。?/td> | 2599K |
| 代理商： | NT5CB256M4AN-BF |
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1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
24
REV 1.2
01 / 2009
DLL-off Mode
DDR3 DLL-
off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set back to
“0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is
specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are
supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship
(tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the DLL-off
mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small compared to
tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on
mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
DLL-off mode READ Timing Operation
Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the
same way and the skew between all DQ, DQS, and DQS# signals will still be tDQSQ.
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
READ
CMD
Bank, Col b
Address
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQSdiff_DLL_on
DQ_DLL_on
DQSdiff_DLL_off
DQ_DLL_off
DQSdiff_DLL_off
DQ_DLL_off
RL = AL+CL = 6 (CL=6, AL=0)
RL(DLL_off) = AL+(CL-1) = 5
tDQSCKDLL_diff_min
tDQSCKDLL_diff_max
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
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| NT5SV8M8DT-7 | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NTC1111-20MHZ | Analog IC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| NT5CB256M8FN-DI | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5CB256M8GN-CG | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16DP-CF | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5CB64M16FP-DH | 制造商:Nanya Technology Corporation 功能描述:MEMORY |
| NT5CB64M16FP-DII | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
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