參數(shù)資料
型號: NT5CB256M4AN-BF
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: DDR DRAM, PBGA78
封裝: 0.80 MM PITCH, ROHS COMPLIANAT, WBGA-78
文件頁數(shù): 15/106頁
文件大小: 2599K
代理商: NT5CB256M4AN-BF
1Gb DDR3 SDRAM A-Die
NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP
16
REV 1.2
01 / 2009
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive latency,
WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on
, , , high on BA0 and low on BA1
and BA2, while controlling the states of address pins according to the following figure.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
Address Filed
DLL
Enable
A0
Enable
0
Disable
1
DLL
Output Driver
Impedance Control
MR
BA0
BA1
MR0
0
MR1
1
0
Mode Register
0
1
MR3
MR2
Qoff
*
* BA2, A5, A8, A10, and A13 are reserved for future use and must be
set to 0 when programming the MR.
** Outputs disabled
– DQs, DQSs, DQSs.
*** In Write leveling Mode (MR1[bit7]=1) with MR1[bit12]=1, all RTT_Nom
settings are allowed; in Write Leveling Mode (MR1[bit7]=1) with
MR1[bit12]=0, only RTT_Nom settin gof RZQ/2, RZQ/4, and RZQ/6 are
allowed.
**** If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4, RZQ/6
are allowed.
Qoff
A12
Output buffer enabled
0
Output buffer disabled
1
AL
A3
A4
0 (AL disable)
0
CL-1
1
0
Additive Latency
0
1
Rtt_Nom
A2
A6
A9
ODT Disable
0
1
0
1
0
1
0
1
0
1
0
1
ODT value
RZQ/4
RZQ/2
RZQ/6
RZQ/12
RZQ/8
Reserved
*
CL-2
Reserved
*
Write Levelization
Write leveling enable
A7
Disabled
0
Enabled
1
TDQS
TDQS enable
A11
Disabled
0
Enabled
1
D.I.C.
A1
A5
Reserved for
RZQ/6
0
RZQ/7
1
0
1
RZQ/TBD
**
***
Note: RZQ=240ohms
****
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