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參數(shù)資料
| 型號： | NCV8881PWR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 321K |
| 描述： | IC REG TRPL BUCK/LINEAR 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（2） |
| 功能： | 車載 |
| 輸出數(shù)： | 3 |
| 頻率 - 開關(guān)： | 170kHz |
| 電壓/電流 - 輸出 1： | 3.3 V ~ 8 V，1.5A |
| 電壓/電流 - 輸出 2： | 5V，100mA |
| 電壓/電流 - 輸出 3： | 8.5V，40mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 5 V ~ 19 V |
| 工作溫度： | -40°C ~ 150°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NCV8881PWR2GOSDKR |
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NCV8881
http://onsemi.com
4
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
1
IGNBUF
This open drain output is pulled low whenever the EN signal is latched and a low level is recognized at
the EN input.
2
WDI
CMOS compatible Watchdog pulse input from a CPU. To be valid, the time between falling edges of this
signal must be less than the programmed Watchdog Delay.
3
RDLY
Delay programming pin for POR, BOOT and Watchdog delays. Connect a resistor between this pin and
ground.
4
RESB
This is an open drain output for resetting a CPU. RESB goes low if the WDI signal period is longer than
the programmed Watchdog delay, if VIN is above or below operating voltage, if the SMPS output is out of
regulation, or if the part is in thermal shutdown.
5
EN
Logic compatible Enable input. Once a high is received at the EN pin, the part enters a startup
sequence. Until expiration of the SoftStart Timer, a low at the EN pin will shut off the part. Upon
expiration of the SoftStart Timer, a low at the EN pin will shut the part off only if the SMPS output is out
of regulation, or the signal at the WDI input is not valid.
6
SYNC
Logic compatible Synchronization input. Grounding this input allows a resistor between the ROSC pin
and ground to control the switching frequency. Connecting this pin to an external clock synchronizes
switching to the rising edge of the clock.
7
ROSC
Oscillator frequency programming pin. Connect an external resistor from this pin to GND to set the
switching frequency. Leave this pin floating to operate at the default frequency of the internal oscillator.
Switching frequency is not controlled by this resistance if a clock is present at the SYNC pin, but the
resistance remains in control of the modulator ramp amplitude.
8
GND
Battery return, and ground reference for output voltages.
9
COMP
Switching Regulator Error Amplifier output for tailoring SMPS transient response with external
compensation components.
10
FB
Feedback input pin to program Switching Regulator output voltage, and detect a low or shorted SMPS
output condition.
11
BST
Bootstrap input provides drive voltage higher than VIN to the SMPS Nchannel Power Switch for
minimum switch R
DS(on)
and highest efficiency. For a typical application connect a 0.1 mF ceramic
capacitor from this pin to the SW pin, in close proximity to both pins.
12
SW
Switching node of the Switching Regulator. Connect the SMPS output inductor and cathode of the SMPS
freewheeling diode to this pin.
13
VIN
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
14
8P5
Output of the internal 8.5 V linear regulator. This provides regulated gate drive voltage to the SMPS
Power Switch. For a typical application connect a 4.7 mF ceramic capacitor in series with 0.5 W from this
pin to ground.
15
LDOMON
This open drain output is pulled low if either the 5P0 or 8P5 output is out of regulation.
16
5P0
Output of the internal 5 V linear regulator. For a typical application connect a 4.7 mF ceramic capacitor in
series with 0.5 W from this pin to ground.
EXPOSED
PAD
Solder this to a low thermal impedance path for cooling.
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