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參數(shù)資料
| 型號： | NCP1927DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 531K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOIC |
| 標準包裝： | 2,500 |
| 系列： | * |
NCP1927
http://onsemi.com
22
Go To Standby Pin
The Go To Standby (GTS) pin is used to disable the PFC
stage during system standby based on the flyback stage load
condition. This can be done by connecting it to the flyback
stage feedback pin (FFB) through a resistor divider or by
directly driving the pin with an optocoupler. These
implementations are shown in Figures 29 and 30.
The GTS pin contains an internal pull down resistor, R
GTS
(typically 200 kW), for use with an optocoupler and to
ensure the PFC is disabled if the pin is floating.
Figure 29. GTS Implementation with Feedback Pin
GTS
FFB
R
GTS1
R
GTS2
C
GTS
The resistor divider from the FFB pin is used to setup the
GTS power level threshold. When V
GTS
is brought below
the GTS threshold, V
standby
, the PFC controller stops
switching and enter standby mode. It remains in standby
until V
GTS
is brought above the hysteresis of V
standby
(V
standby(HYS)
). A timer is included on the GTS pin to ensure
transients on the flyback converter do not trigger GTS.
However, the PFC must come out of standby as soon as
possible if there is a request to turn on the TV. Therefore, the
timer is bypassed when coming out of standby. The FFB
voltage at which the PFC enters GTS is expressed using
Equation 21.
V
FFB(GTS)
+ V
GTS
@
R
GTS1
) R
equiv
R
equiv
(eq. 21)
where R
equiv
is the parallel resistor combination of R
GTS
and
R
GTS2
and is calculated using Equation 22.
R
equiv
+
R
GTS
@ R
GTS2
R
GTS
) R
GTS2
(eq. 22)
If direct control of the PFC standby mode is desired, the
GTS pin can instead be driven with an optocoupler from the
secondary side to force the PFC stage in and out of standby
mode. A resistor (R
limit
) is placed in series with the
optocoupler to limit the current into the GTS pin.
Figure 30. GTS Implementation with Optocoupler
VCC_AUX
GTS
C
GTS
from secondary side
R
limit
IENABLE Pin
The IENABLE pin is designed to drive an optocoupler
that enables the Flat Panel TV backlight inverter once the
PFC stage reaches regulation. The NCP1927 achieves this
by monitoring the current sourced by the EA. Once this
current drops to 0 mA, the IENABLE pin voltage switches
to V
IENABLE(high)
(typically 5.0 V). This operation is shown
in Figure 31.
Figure 31. IENABLE Pin Timing
time
V
out
V
out(MAX)
time
V
IENABLE
5 V
0 V
V
out(MIN)
V
out(NOM)
time
I
EA(out)
0 糀
20 糀
Inverter
Starts
Undershoot from Inverter
Load
A separate comparator on the PFB pin is used to protect
the inverter from undervoltage conditions by detecting
when the PFB voltage falls below V
disable
. When this occurs,
the IENABLE pin voltage switches to V
IENABLE(low)
. Using
the result from Equation 7, the output threshold that sets the
IENABLE pin low can be calculated with Equation 23.
V
out(disable)
+
V
out
@ V
disable
V
REF
(eq. 23)
where V
disable
is the disable threshold (1.865 V typical).
The IENABLE pin can also be used as a voltage reference.
To filter noise, a decoupling capacitor (C
REF
) may be
connected to the pin.
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