參數(shù)資料
型號(hào)： NCP1927DR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 21/24頁(yè)
文件大小： 531K
描述： IC CTLR PFC/FLYBACK 16-SOIC
標(biāo)準(zhǔn)包裝： 2,500
系列： *
NCP1927
http://onsemi.com
21
Skip Mode Operation
The NCP1927 automatically skips switching cycles when
the power demand drops below a given level. This is
accomplished by monitoring the internal offset PControl
voltage. This voltage is compared to the PCT ramp to control
the power level in a particular design. During normal
operation, the circuit generates the input line current
necessary for matching the load power demand. If the need
for power decreases, the regulation loop lowers the
regulation voltage to reduce the power delivery accordingly.
When the regulation voltage goes below a programmable
preset level, the PFC stage stops switching. This causes the
output voltage to decrease, and the regulation voltage to
increase. When the regulation voltage exceeds the skip
threshold, switching resumes.
This operation allows the PFC stage to deliver 10% power
for 10% of the time, as opposed to 1% power for 100% of the
time. This skip cycle mode, also called controlled burst
operation, is much more efficient than a continuous power
flow since it drastically reduces the number of switching
pulses and their associated switching losses. To ensure
stability, hysteresis is added.
The PSKIP pin provides the possibility to adjust these
levels by connecting it through a single resistor to ground.
Since the skip threshold power levels can vary with line
voltage, they are calculated using Equations 18 and 19.
P
skip(lower)
+
V
PSKIP
5 V @
Vac
LL
Vac
2
@ P
out(MAX)
(eq. 18)
P
skip(upper)
+
V
PSKIP
4.5 V @
Vac
LL
Vac
2
@ P
out(MAX)
(eq. 19)
where V
PSKIP
 is the voltage applied to the PSKIP pin, Vac
LL
is the minimum ac line voltage, Vac is the operating line
voltage, and P
out(MAX)
 is the maximum output power.
The skip pin voltage is adjusted through a resistor to
ground using Equation 20.
V
PSKIP
+ I
PSKIP
@ R
PSKIP
(eq. 20)
where I
PSKIP
 is the value of the internal current source
(30 mA typical) and R
PSKIP
 is the external resistor connected
to ground.
If desired, skip mode can be easily disabled by connecting
the PSKIP pin directly to ground. If the PSKIP pin is left
floating, V
PSKIP
 will rise towards the internal voltage rail
and disable the drive. Since the PControl Pin is low during
startup, the PFC skip mode is disabled until the PFC output
reaches regulation and the IENABLE Pin is high. A
simplified schematic of the PSKIP pin is shown in
Figure 28.
Figure 28. Schematic for PSKIP Pin
9*R
R
PControl
PFC_OK
OTA Output
PFAULT
To PWM Comparator
SKIP
PSKIP
R
PSKIP
V
DD
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