參數(shù)資料
型號： NCP1605DR2G
廠商： ON Semiconductor
文件頁數(shù)： 21/32頁
文件大?。?/td> 745K
描述： IC PFC CONTROLLER CCM/DCM 16SOIC
標準包裝： 1
系列： Soft-Skip™
模式： 臨界傳導（CRM），間歇導電（DCM）
頻率 - 開關： 250kHz
電流 - 啟動： 12mA
電源電壓： 10 V ~ 20 V
工作溫度： 0°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 16-SOIC
包裝： 標準包裝
其它名稱： NCP1605DR2GOSDKR
NCP1605, NCP1605A, NCP1605B
http://onsemi.com
21
pfcOK signal of the block diagram, is high). This is
because, at the beginning of operation, the Pin 3 capacitor
must charge slowly and gradually for a softstartup.
Remark: As shown in block diagram, the circuitry for
undershoots limitation is disabled as long as Pin 3 detects
standby conditions (V
Pin3
 < 300 mV). This is to suppress the
risk of audible noise in standby thanks to the softstart that
softens the bursts.
OnTime Control for Maximum Power Adjustment
As aforementioned, the NCP1605 processes the error
amplifier output voltage to form a signal (V
TON
) that is used
by the PWM section to control the ontime. (V
TON
)
compensates the relative weight of the deadtime sequences
measured during the precedent current cycles. During the
conduction time of the MOSFET, Pin 7 sources a current that
is proportional to the square of the voltage applied to Pin 4
(feedback pin). Practically, as Pin 4 receives a portion of the
output voltage (V
OUT
), I
Pin7
 is proportional to the square of
V
OUT
.
The MOSFET turns off when the Pin 7 voltage exceeds
V
TON
. Hence, the MOSFET ontime (t1) is given by:
t
1
+
C
pin7
V
TON
k V
OUT
2
where k is a constant.
The coil current averaged over one switching period is:
t I
COIL
u
T
+ I
IN
(t) +
V
IN
t
1
2 L
(t
1
) t
2
)
T
Where I
IN
(t) and V
IN
(t) are the instantaneous input current
and voltage, respectively, t
2
 is the core reset time and T is the
switching period. Hence, the instantaneous input power is
given by the following equation:
P
IN
(t) + V
IN
(t)I
IN
(t) +
C
pin7
V
IN
2
2 L k V
OUT
2
@
V
TON
(t
1
) t
2
)
T
As aforementioned, we have: V
TON
 (t
1
 + t
2
)/T = V
REGUL
where V
REGUL
  is the signal outputted by the regulation
block. Hence, the average input power is:
t P
IN
u+
C
pin7
V
ac
2
2 L k V
OUT
2
V
REGUL
The maximum value of V
REGUL
 being 1 V, the maximum
power that can be delivered is:
t P
IN
u
MAX
+
C
pin7
V
ac
2
2 L k V
OUT
2
1 V
To the light of the last equations, one can note that the PFC
power capability is inversely proportional to the square of the
output voltage. One sees that if the power demand is too high
to keep the regulation, (V
REGUL
=1V) and the power delivery
depends on the output voltage level that stabilizes to the
following value:
V
OUT
+
C
pin7
1 V
2 L k h P
OUT
V
ac
Where:
" P
OUT
 is the output power.
" And h is the efficiency.
Hence, one obtains the Follower Boost characteristics. The
Follower Boost   is an operation mode where the
preconverter output voltage stabilizes at a level that varies
linearly versus the ac line amplitude. This technique aims at
reducing the gap between the output and input voltages to
optimize the boost efficiency and minimize the cost of the
PFC stage (refer to the MC33260 data sheet for more
information, at:
http://www.onsemi.com/pub/Collateral/MC33260D.PDF ).
Remark:  the  timing  capacitor  applied  to  Pin  7  is
discharged and maintained grounded when the drive is low.
Furthermore, the circuit compares the Pin 7 voltage to an
internal reference 50 mV and prevents the PWM latch from
being set as long as V
Pin7
 is higher than this low threshold.
This is to guarantee that the timing capacitor is properly
discharged before starting a new cycle.
Current Sense and Zero Current Detection
The NCP1605 is designed to monitor a negative voltage
proportional to the coil current. Practically, a current sense
resistor (R
CS
) is inserted in the return path to generate a
negative voltage proportional to the coil current (V
CS
). The
circuit uses V
CS
 for  two  functions:  the  limitation  of  the
maximum coil current and the detection of the core reset
(coil demagnetization). To do so, the circuit incorporates
an operational amplifier that sources the current necessary
to maintain the CS pin voltage null (refer to Figure 60). By
inserting a resistor R
OCP
 between the CS pin and R
CS
, we
adjust the CS pin current as follows:
* [R
CS
I
COIL
] ) [R
OCP
I
pin5
] + V
pin5
[ 0
Which leads to:
I
pin5
+
R
CS
R
OCP
I
COIL
In other words, the Pin 5 current is proportional to the coil
current.
I
Pin5
 is utilized as follows:
" If I
Pin5
 exceeds 250 mA, an overcurrent is detected and
the PWM latch is reset. Hence, the maximum coil
current is:
(I
COIL
)max +
R
OCP
R
CS
250 mA
The propagation delay (Ipin5 higher than 250 mA) to
(drive output low) is in the range of 100 ns, typically.
" The Pin 5 current is internally copied and sourced by
Pin 6. Place a resistor (R
Pin6
) between Pin 6 and ground
to build a voltage proportional to the coil current. The
circuit detects the core reset when V
Pin6
 drops below
100 mV, typically. The Pin 6 voltage equating:
V
pin6
+
R
pin6
@ R
cs
R
cs
@ I
COIL
,
the coil current threshold for zero current detection is:
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