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| 型號(hào)： | NCP1605DR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 19/32頁(yè) |
| 文件大?。?/td> | 745K |
| 描述： | IC PFC CONTROLLER CCM/DCM 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Soft-Skip™ |
| 模式： | 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM） |
| 頻率 - 開(kāi)關(guān)： | 250kHz |
| 電流 - 啟動(dòng)： | 12mA |
| 電源電壓： | 10 V ~ 20 V |
| 工作溫度： | 0°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NCP1605DR2GOSDKR |
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NCP1605, NCP1605A, NCP1605B
http://onsemi.com
19
Figure 53. PFC Boost Converter
Figure 54. Inductor Current in DCM
L
I
in
V
in
V
out
Time
Inductor Current
I
pk
T
t
1
t
2
t
3
The NCP1605 operates in voltage mode. As portrayed by
Figure 55, the MOSFET on time t
1
is controlled by the
signal V
ton
generated by the regulation block and the Pin
4 ramp as follows:
t
1
+
C
pin7
@ V
TON
I
pin7
(eq. 2)
The charge current that is sourced by Pin 7
[I
pin7
= 60 mA/V
2
* (V
Pin4
)
2
] is constant at a given input
voltage (V
Pin4
is proportional to the output voltage). C
pin7
that is the capacitor connected between Pin 7 and ground
is also a constant. Hence, the power factor correction is
achieved when the V
TON
(t
1
+ t
2
)/T term is constant.
The output of the regulation block (V
CONTROL
) is
linearly changed into a signal (V
REGUL
) varying between
0 and 1 V. (V
REGUL
) is the voltage that is injected into the
PWM section to modulate the MOSFET dutycycle.
However, like the NCP1601, the NCP1605 inserts some
circuitry that processes (V
REGUL
) to form the signal
(V
TON
) that is used in the PWM section instead of
(V
REGUL
) (see Figure 56). (V
TON
) is modulated in response
to the deadtime sensed during the precedent current
cycles, that is, for a proper shaping of the ac line current
(refer to NCP1601 data sheet). This modulation leads to:
V
TON
+
T @ V
REGUL
t
1
) t
2
or : V
TON
@
t
1
) t
2
T
+ V
REGUL
(eq. 3)
Given the regulation low bandwidth of the PFC systems,
(V
CONTROL
) and then (V
REGUL
) are slow varying signals.
Hence, the (V
TON
* (t
1
+ t
2
)/T) term is substantially
constant. Provided that in addition, (t1) is proportional to
(V
TON
), equation (1) leads to: (I
in
= k * V
in
), where k is a
constant. More exactly:
I
in
+ k @ V
in
(eq. 4)
where : k + constant +
C
pin7
@ V
REGUL
120 m @ L @ (V
pin2
)
2
The input current is then proportional to the input
voltage. Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CRM
case. This condition is just a particular case of this
functioning where (t
3
= 0), which leads to (t
1
+ t
2
= T) and
(V
TON
= V
REGUL
). That is why the NCP1605 automatically
adapts to the conditions and jumps from DCM and CRM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
Remark: Like in the NCP1601, the V
TON
processing
circuit is informed when there is an OVP condition, not
to overdimension V
TON
in that conditions. Otherwise, an
OVP sequence would be viewed as a deadtime phase by
the circuit and V
TON
would inappropriately increase to
compensate it.
Similarly, the V
TON
processing circuit is inhibited for
a skip sequence not to overdimension V
TON
in this case
(refer to Figure 56).
Figure 55. PWM Circuit and Timing Diagram
Figure 56. V
TON
Processing Circuit
+
> Vton during (t1+t2)
> 0 V during t3 (deadtime)
> Vton*(t1+t2)/T in average
+
timing capacitor
sawtooth
to PWM latch
PWM
comparator
IN1
S1
S2
C1
R1
SKIP
OVP
OA1
OFF
S3
DT
(high during
deadtime)
The integrator OA1 amplifies the error between V
REGUL
and
IN1 so that in average, (V
TON
*(t1+t2)/T) equates V
REGUL
.
V
REGUL
V
ton
V
ton
Ramp Voltage
PWM Outtage
Turns Off MOSFET
V
ton
C
ramp
I
ch
PWM Comparator
Closed When
Output Low
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