參數資料
| 型號： | NCN6000DTBR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 8/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 產品變化通告： | Product Obsolescence 01/Jul/2009 |
| 標準包裝： | 1 |
| 應用： | ATM 終端，氣泵，ISM |
| 接口： | 微控制器 |
| 電源電壓： | 2.7 V ~ 6 V |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
16
Programming Mode
The programming mode allows the configuration of the
card power supply, card clock and Card Detection input
logic polarity. These signals (CRD_VCC, CRD_CLK and
CRD_DET) are described in the pin description paragraph
Programming Mode
Logic Conditions:
Card Output:
CS
= L
PWR_ON = L
A0
= H/L
A1
= H/L
PGM
= L
I/O
= L/H
RESET
= L/H
CRD_VCC = 0 V
CRD_CLK = L
CRD_RST = L
CRD_IO
= H/L depending upon
the previous I/O pin
logic state
The I/O and RESET pins are not connected to the smart
card and become logic inputs to control the NCN6000
programming sequence. The programmed values are
latched upon transition of CS from Low to High, PGM being
Low during the transition.
When a programming mode is validated by a Chip Select
negative going transient, the mode is latched and PGM can
be released to High. This latch is automatically reset when
CS returns to High.
The logic input signals can be set simultaneously, or one
bit a time (using either a STAA or a BSET function), the key
point being the minimum delay between the shorter bit and
the Chip Select pulse. The programmed value is latched into
the NCN6000 register on the CS positive going edge.
PROGRAMMING
2
ms2 ms
1
ms
NORMAL MODE
PGM
I/O
A0
A1
RESET
CS
Figure 8. Minimum Programming Timings
Active Mode
In the active mode, the NCN6000 is selected by the
external MPU and the STATUS pin can be polled to get the
status of either the DCDC converter or the presence of the
card (inserted or not valid). The power is not connected to
the card: CRD_VCC = 0 V.
Active Mode
Logic Conditions:
Card Output:
CS
= L
PWR_ON = L
A0
= L
A1
= L
PGM
= H
I/O
= Z
RESET
= Z
STATUS
= L/H is Card
Inserted?
CRD_VCC = 0 V
CRD_CLK = L
CRD_RST = L
CRD_IO
= H/L depending upon
the previous I/O pin
logic state
The Chip Select pulse [CS] will automatically clear the
previously asserted INT signal upon the positive going
transition.
If a card is present, the MPU shall activate the DCDC
converter by asserting PWR_ON = H. The NCN6000 will
automatically run a power up sequence when the
CRD_VCC reaches the undervoltage level (either VC5H or
VC3H, depending upon the CRD_VCC voltage supply
programmed). The CRD_IO, CRD_RST and CRD_CLK
pins are validated, according to the ISO78163 sequence.
The interface is now in transaction mode and the system is
ready for data exchange through the I/O and RESET lines.
At any time, the microcontroller can change the CRD_CLK
frequency and mode, or the CRD_VCC value as determined
by the card being in use.
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