參數(shù)資料
型號(hào)： NCN6000DTBR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 32/36頁(yè)
文件大小： 0K
描述： IC INTERFACE SMART CARD 20TSSOP
產(chǎn)品變化通告： Product Obsolescence 01/Jul/2009
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： ATM 終端，氣泵，ISM
接口： 微控制器
電源電壓： 2.7 V ~ 6 V
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 剪切帶 (CT)
安裝類(lèi)型： 表面貼裝
其它名稱(chēng)： NCN6000DTBR2GOSCT
NCN6000
http://onsemi.com
5
The programming can be achieved with the card powered
ON or OFF. The identification of the interrupt is carried out
by polling the STATUS pin, the Vbat voltage and the
DCDC results being provided on the same pin as depicted
by the table in Figure 4. During the programming mode, the
PGM pin can be released to High since the mode is internally
latched by the Negative going transition presents on the Chip
Select pin.
PGM
INT
CRD_DET
CARD EXTRACTED
CARD IDENTIFICATION
POLLING
50
ms
INTERRUPT
ACKNOWLEDGE
50
ms
High
Low
CS
A0
A1
STATUS
S1 CLEAR INTERRUPT
S2 CARD PRESENT: STATUS = 1
S3 CLEAR INTERRUPT
S4 CARD PRESENT: STATUS = 0
Figure 5. Interrupt Servicing and Card Polling
When a card is either inserted or extracted, the CRD_DET
pin signal is debounced internally prior to pull the INT pin
to
Low.
The
builtin
logic
circuit
automatically
accommodates positive or negative input signal slope, on
both insertion and extraction state, depending upon the
polarity defined during the initialization sequence. The
default condition is Normally Open switch, negative going
card detection. The external CPU shall acknowledge the
request by forcing CS = L which, in turn, releases the INT
pin to High upon positive going of Chip Select (Table 4).
Polling the STATUS pin as depicted in Table 3 identifies the
active card. If a card is present, the STATUS returns High,
otherwise a Low is presented pin 5. The 50
ms digital filter
is activated during both Insertion and Extraction of the card.
The MPU shall clear the INT line when the card has been
extracted, making the interrupt function available for other
purposes. However, neither the NCN6000 operation nor the
smart card I/O line or commands are affected by the state of
the INT pin.
On the other hand, clearing the INT and reading the
STATUS register can be performed by a single read by the
MPU: states S1 and S2 can be combined in a single
instruction, the same for S3 and S4.
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