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參數(shù)資料
| 型號(hào)： | NCN6000DTBR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 產(chǎn)品變化通告： | Product Obsolescence 01/Jul/2009 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | ATM 終端，氣泵，ISM |
| 接口： | 微控制器 |
| 電源電壓： | 2.7 V ~ 6 V |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
21
Power Management
The purpose of the power management is to activate the
circuit functions needed to run a given mode of operation,
yielding a minimum current consumption on the Vbat
supply. In the Standby mode (PWR_ON = L), the power
management provides energy to the card detection circuit
only. All the card interface pins are forced to ground
potential.
In the event of a power up request coming from the
external MPU (PWR_ON = H, CS = L), the power manager
starts the DCDC converter.
When the CRD_VCC voltage reaches the programmed
value (3.0 V or 5.0 V), the circuit activates the card signals
according to the following sequence:
CRD_VCC
CRD_IO
CRD_CLK
CRD_RST
The logic level of the data lines are asserted High or Low,
depending upon the state forced by the external MPU, when
the start up sequence is completed. Under no situation the
NCN6000 shall launch automatically a smart card ATR
sequence. Assuming PWR_ON = H, the CRD_VCC voltage
is maintained whatever be the logic level presents on Chip
Select, pin 6.
At the end of the transaction, asserted by the MPU
(PWR_ON = L, CS = L), or under a card extraction, the
ISO78163 power down sequence takes place:
CRD_RST
CRD_CLK
CRD_IO
CRD_VCC
When CS = H, the bidirectional I/O line (pins 8 and 15)
is forced into the High impedance mode to avoid signal
collision with any data coming from the external MPU.
The CRD_VCC voltage is controlled by means of CS and
PWR_ON logic signal as depicted in Figure 14. The
PWR_ON logic level define the CRD_VCC voltage status,
the amplitude being the one pre programmed into the chip.
In order to avoid uncontrolled command applied to the
smart card, the NCN6000 internal logic circuit, together
with the Vbat monitoring, clamps the card outputs until the
CRD_VCC voltage reaches the minimum value. During the
CRD_VCC slope, all the card outputs are kept Low and no
spikes can be write to the smart card. The oscillogram on the
right hand side is a magnification of the curves given on the
opposite side.
CS
PWR_ON
CRD_VCC
CRD_VCC Rise Time
CRD_VCC No Change
CRD_VCC Power Down Fall Time
CRD_VCC No Change
250
ms
2 ms
Figure 14. Card Power Supply Control
Figure 15. Smart Card Signals Sequence at Power On
CRD_VCC
CRD_CLK
CP = 15 pF
CRD_RST
CRD_IO
5.0 V
CRD_VCC
CRD_CLK
CRD_RST
CRD_IO
5.0 V
CP = 15 pF
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| NCN6001DTBEVB | 功能描述:界面開發(fā)工具 NCN6001 TSSOP EVAL BOARD RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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