參數(shù)資料
型號(hào): NB6N14S
廠商: ON SEMICONDUCTOR
英文描述: 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator(3.3V,1:4任一級(jí)差分輸入到LVDS輸出緩沖器/轉(zhuǎn)換器)
中文描述: 3.3伏1:4 AnyLevel的LVDS差分輸入的扇出緩沖器/翻譯器(3.3V,1:4任一級(jí)差分輸入到的LVDS輸出緩沖器/轉(zhuǎn)換器)
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 110K
代理商: NB6N14S
NB6N14S
http://onsemi.com
5
Table 6. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND
= 0 V; (Note 12)
Symbol
Characteristic
40
°
C
25
°
C
85
°
C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
inMax
Maximum Input Clock Frequency
2.0
2.0
2.0
GHz
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)f
in
1.0 GHz
(Figure 4)
f
in
= 1.5 GHz
f
in
= 2.0 GHz
220
200
170
350
300
270
220
200
170
350
300
270
220
200
170
350
300
270
mV
f
DATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
t
PLH
,
t
PHL
Differential Input to Differential Output
Propagation Delay
300
450
600
300
450
600
300
450
600
ps
t
s
t
h
Setup Time
Hold Time
300
500
60
70
300
500
60
70
300
500
60
70
t
SKEW
Within Device Skew (Note 17)
DevicetoDevice Skew (Note 16)
5
30
20
200
5
30
20
200
5
30
20
200
ps
t
JITTER
RMS Random Clock Jitter (Note 14)
f
in
= 1.0 GHz
f
= 1.5 GHz
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
Deterministic Jitter (Note 15)
0.5
0.5
10
10
10
0.5
0.5
10
10
10
0.5
0.5
10
10
10
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
100
V
GND
100
V
GND
100
V
GND
mV
t
r
t
f
Output Rise/Fall Times @ 250 MHz
(20% 80%)
Q, Q
60
120
190
60
120
190
60
120
190
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Measured by forcing V
with 50% duty cycle clock source and V
CC
1400 mV offset. All loading with an external R
L
= 100 . Input
edge rates 150 ps (20%80%). See Figure 13.
13.Input voltage swing is a singleended measurement operating in differential mode.
14.RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15.Deterministic jitter with input NRZ data at PRBS 2
23
1 and K28.5.
16.Skew is measured between outputs under identical transition @ 250 MHz.
17.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 3.3 V)
O
(
0
50
100
150
200
250
300
350
400
0.5
1
1.5
2
2.5
3
0
85
°
C
40
°
C
25
°
C
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