參數(shù)資料
型號(hào): NB6N14S
廠商: ON SEMICONDUCTOR
英文描述: 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator(3.3V,1:4任一級(jí)差分輸入到LVDS輸出緩沖器/轉(zhuǎn)換器)
中文描述: 3.3伏1:4 AnyLevel的LVDS差分輸入的扇出緩沖器/翻譯器(3.3V,1:4任一級(jí)差分輸入到的LVDS輸出緩沖器/轉(zhuǎn)換器)
文件頁數(shù): 1/10頁
文件大?。?/td> 110K
代理商: NB6N14S
Semiconductor Components Industries, LLC, 2006
May, 2006 Rev. 2
1
Publication Order Number:
NB6N14S/D
NB6N14S
3.3 V 1:4 AnyLevel
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevel differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to V
CC
50 mV. Combined with the 50
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or singleended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16QFN
package. Application notes, models, and support documentation are
available at
www.onsemi.com
.
The NB6N14S is a member of the ECLinPS MAX family of high
performance products.
internal
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
V
REF_AC
Reference Output
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are PbFree Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
231
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
V
(
Device DDJ = 10 ps
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
16
NB6N
14S
ALYW
1
1
Q3
Q3
Figure 1. Logic Diagram
Q2
Q2
Q1
Q1
Q0
Q0
EN
(LVTTL/CMOS)
V
REF_AC
D
Q
50
50
IN
VT
/IN
(Note: Microdot may be in either location)
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