參數(shù)資料
型號: NB6N14S
廠商: ON SEMICONDUCTOR
英文描述: 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator(3.3V,1:4任一級差分輸入到LVDS輸出緩沖器/轉(zhuǎn)換器)
中文描述: 3.3伏1:4 AnyLevel的LVDS差分輸入的扇出緩沖器/翻譯器(3.3V,1:4任一級差分輸入到的LVDS輸出緩沖器/轉(zhuǎn)換器)
文件頁數(shù): 2/10頁
文件大小: 110K
代理商: NB6N14S
NB6N14S
http://onsemi.com
2
Figure 3. NB6N14S Pinout, 16pin QFN
(Top View)
Q3
Q3
V
CC
EN
GND
IN
V
T
V
REF_AC
IN
Q1
Q1
Q2
Q2
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB6N14S
Exposed Pad (EP)
Q0
Q0
V
CC
IN
IN
EN
Q
0
1
1
0
1
0
1
1
x
x
0
0 (Note 1)
1. On next transition of the input signal (IN).
Table 1. TRUTH TABLE
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 receiver termination
resistor across differential pair.
2
Q1
LVDS Output
Inverted IN output. Typically loaded with 100 receiver termination resistor
across differential pair.
3
Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 receiver termination
resistor across differential pair.
4
Q2
LVDS Output
Inverted IN output. Typically loaded with 100 receiver termination resistor
across differential pair.
5
Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 receiver termination
resistor across differential pair.
6
Q3
LVDS Output
Inverted IN output. Typically loaded with 100 receiver termination resistor
across differential pair.
7
V
CC
EN
Positive Supply Voltage.
8
LVTTL / LVCMOS Input
Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 19. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10
V
REF_AC
LVPECL Output
The V
REF_AC
reference output can be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, V
REF_AC
should be connected to the VT pin and bypassed to
ground with a 0.01 F capacitor.
11
V
T
IN
LVPECL Output
Internal 100 Centertapped Termination Pin for IN and IN
12
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13
GND
Negative Supply Voltage.
14
V
CC
Q0
Positive Supply Voltage.
15
LVDS Output
Noninverted IN output. Typically loaded with 100 receiver termination
resistor across differential pair.
16
Q0
LVDS Output
Inverted IN output. Typically loaded with 100 receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
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