參數(shù)資料
型號: NB6N14S
廠商: ON SEMICONDUCTOR
英文描述: 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator(3.3V,1:4任一級差分輸入到LVDS輸出緩沖器/轉(zhuǎn)換器)
中文描述: 3.3伏1:4 AnyLevel的LVDS差分輸入的扇出緩沖器/翻譯器(3.3V,1:4任一級差分輸入到的LVDS輸出緩沖器/轉(zhuǎn)換器)
文件頁數(shù): 4/10頁
文件大?。?/td> 110K
代理商: NB6N14S
NB6N14S
http://onsemi.com
4
Table 5. DC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= 40
°
C to +85
°
C
Symbol
Characteristic
Min
Typ
Max
Unit
I
CC
Power Supply Current (Note 9)
65
100
mA
DIFFERENTIAL INPUTS DRIVEN SINGLEENDED
(Figures 10, 11, 15, and 17)
V
th
Input Threshold Reference Voltage Range (Note 8)
GND +100
V
CC
100
mV
V
IH
Singleended Input HIGH Voltage
V
th
+ 100
V
CC
mV
V
IL
Singleended Input LOW Voltage
GND
V
th
100
mV
V
REF_AC
Reference Output Voltage (Note 11)
V
CC
1.600
V
CC
1.425
V
CC
1.300
V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 6, 7, 8, 9, 16, and 18)
V
IHD
Differential Input HIGH Voltage
100
V
CC
mV
V
ILD
Differential Input LOW Voltage
GND
V
CC
100
mV
V
CMR
Input Common Mode Range (Differential Configuration)
GND + 50
V
CC
50
mV
V
ID
Differential Input Voltage (V
IHD
V
ILD
)
100
V
CC
mV
R
TIN
Internal Input Termination Resistor
40
50
60
LVDS OUTPUTS
(Note 5)
V
OD
Differential Output Voltage
250
450
mV
V
OD
Change in Magnitude of V
OD
for Complementary Output States
(Note 10)
0
1
25
mV
V
OS
Offset Voltage (Figure 14)
1125
1375
mV
V
OS
Change in Magnitude of V
OS
for Complementary Output States
(Note 10)
0
1
25
mV
V
OH
Output HIGH Voltage (Note 6)
1425
1600
mV
V
OL
Output LOW Voltage (Note 7)
900
1075
mV
LVTTL/LVCMOS INPUTS
V
IH
Input HIGH Voltage (Note 7, 8)
2.0
V
CC
V
V
IL
Input LOW Voltage (Note 7, 8)
GND
0.8
V
I
IH
Input HIGH Current
150
150
A
I
IL
Input LOW Current
150
150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVDS outputs require 100 receiver termination resistor between differential pair. See Figure 13.
6. V
OH
max = V
OS
max +
V
OD
max.
7. V
OL
max = V
OS
min
V
OD
max.
8. V
th
is applied to the complementary input when operating in singleended mode.
9. Input termination pins open, D/D at the DC level within V
CMR
and output pins loaded with R
L
= 100 across differential.
10.Parameter guaranteed by design verification not tested in production.
11.V
REF_AC
used to rebias capacitorcoupled inputs only (see Figures 10 and 11).
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