參數(shù)資料
型號: NAND512R3B3BZA6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 64M X 8 FLASH 1.8V PROM, 35 ns, PBGA63
封裝: 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63
文件頁數(shù): 10/59頁
文件大?。?/td> 998K
代理商: NAND512R3B3BZA6E
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
18/59
COMMAND SET
All bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand
Register.
The
two-step
command
sequences for program and erase operations are
imposed to maximize data security.
The
Commands
are
summarized
in
Table 10. Commands
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
2. For consecutive read operations the 00h command does not need to be repeated.
3. Only during Cache Read busy.
Command
Bus Write Operations(1)
Commands
accepted
during busy
1st CYCLE
2nd CYCLE
3rd CYCLE
4th CYCLE
Read
00h(2)
30h
Random Data Output
05h
E0h
Cache Read
00h
31h
Exit Cache Read
34h
Yes(5)
Page Program
(Sequential Input default)
80h
10h
Random Data Input
85h
Copy Back Program
00h
35h
85h
10h
Cache Program
80h
15h
Block Erase
60h
D0h
Reset
FFh
Yes
Read Electronic Signature
90h
Read Status Register
70h
Yes
Read Block Lock Status
7Ah
Blocks Unlock
23h
24h
Blocks Lock
2Ah
Blocks Lock-Down
2Ch
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PDF描述
NAND512W3B3BN6E 64M X 8 FLASH 3V PROM, 35 ns, PDSO48
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