- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄189003 > NAND02GW3B3BN1F (STMICROELECTRONICS) 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 PDF資料下載
參數(shù)資料
| 型號(hào)： | NAND02GW3B3BN1F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 998K |
| 代理商： | NAND02GW3B3BN1F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
21/59
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Read
The Cache Read operation is used to improve the
read throughput by reading data using the Cache
Register. As soon as the user starts to read one
page, the device automatically loads the next page
into the Cache Register.
An Cache Read operation consists of three steps
(see Table 10.):
1.
One bus cycle is required to setup the Cache
Read command (the same as the standard
Read command)
2.
bus cycles are then required to input the Start
Address
3.
One bus cycle is required to issue the Cache
Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a
page (Column Address = 00h, see Table 8. and
Table 9.). This allows the data to be output unin-
The Ready/Busy signal can be used to monitor the
start of the operation. During the latency period the
Ready/Busy signal goes Low, after this the Ready/
Busy signal goes High, even if the device is inter-
nally downloading page n+1.
Once the Cache Read operation has started, the
Status Register can be read using the Read Status
Register command.
During the operation, SR5 can be read, to find out
whether the internal reading is ongoing (SR5 =
‘0’), or has completed (SR5 = ‘1’), while SR6 indi-
cates whether the Cache Register is ready to
download new data.
To exit the Cache Read operation an Exit Cache
Read command must be issued (see Table 10.).
If the Exit Cache Read command is issued while
the device is internally reading page n+1, page n
will still be output, but not page n+1.
Figure 11. Cache Read Operation
I/O
RB
Address
Inputs
ai08661
00h
Read
Setup
Code
31h
Cache
Read
Confirm
Code
Busy
tBLBH1
(Read Busy time)
1st page
Data Output
2nd page
3rd page
last page
34h
Exit
Cache
Read
Code
Block N
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND02GW3B3CN6 | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND04GR3B3BN1F | 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND512W3B3BN1E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3CN6E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3CZA6E | 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND04GR3B2DDI6 | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
| NAND04GR3B2DN6E | 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| NAND04GR3B2DZL6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND04GR3B2EN6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND04GR3B2EN6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。