參數(shù)資料
型號(hào)： N04Q1618C2BW-15C
廠商： ON SEMICONDUCTOR
元件分類(lèi)： SRAM
英文描述： 256K X 16 STANDARD SRAM, 150 ns, UUC
封裝： WAFER
文件頁(yè)數(shù)： 7/13頁(yè)
文件大?。?/td> 305K
代理商： N04Q1618C2BW-15C
Stock No. 23451-D 11/06
3
The specification is ADVANCE INFORMATION and subject to change without notice.
N04Q1618C2B
Advance Information
AMI Semiconductor, Inc.
Functional Block Diagram
Functional Description
CE1
CE2
WE
OE
UB1
LB1
I/O0 - I/O151
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
MODE
POWER
H
X
XX
High Z
Standby2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
X
L
XX
High Z
Standby2
Standby
L
H
X
H
High Z
Standby
LHL
X3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Data In
Write3
Active
LH
HL
Data Out
Read
Active
LH
H
High Z
Active
Capacitance1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
CIN
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
I/O Capacitance
CI/O
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
Address
Inputs
(A1 - A4)
Address
Inputs
(A0, A5 - A17)
Word
Address
Decode
Logic
4Mb
RAM Array
Wo
rd
M
ux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE1
CE2
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
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