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參數(shù)資料
| 型號： | N01L083WC2AT-55I |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP1-32 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 162K |
| 代理商： | N01L083WC2AT-55I |
(DOC# 14-02-008 REV I ECN# 01-1283)
5
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
N01L083WC2A
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Output Load
CL = 30pF
Operating Temperature
-40 to +85 oC
Timing
Item
Symbol
2.3 - 3.6 V
2.7 - 3.6 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
tRC
70
55
ns
Address Access Time
tAA
70
55
ns
Chip Enable to Valid Output
tCO
70
55
ns
Output Enable to Valid Output
tOE
35
30
ns
Chip Enable to Low-Z output
tLZ
10
ns
Output Enable to Low-Z Output
tOLZ
55
ns
Chip Disable to High-Z Output
tHZ
0200
15
ns
Output Disable to High-Z Output
tOHZ
0200
15
ns
Output Hold from Address Change
tOH
10
ns
Write Cycle Time
tWC
70
55
ns
Chip Enable to End of Write
tCW
50
45
ns
Address Valid to End of Write
tAW
50
45
ns
Write Pulse Width
tWP
40
32.5
ns
Address Setup Time
tAS
00
ns
Write Recovery Time
tWR
00
ns
Write to High-Z Output
tWHZ
20
15
ns
Data to Write Time Overlap
tDW
40
30
ns
Data Hold from Write Time
tDH
00
ns
End Write to Low-Z Output
tOW
55
ns
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