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參數(shù)資料
| 型號(hào)： | N01L083WC2AT-55I |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP1-32 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 162K |
| 代理商： | N01L083WC2AT-55I |
(DOC# 14-02-008 REV I ECN# 01-1283)
2
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
AMI Semiconductor, Inc.
N01L083WC2A
Functional Block Diagram
Functional Description
CE1
CE2
WE
OE
I/O0 - I/O7
MODE
POWER
H
X
High Z
Standby1
1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated
from any external influence and disabled from exerting any influence externally.
Standby
X
L
X
High Z
Standby1
Standby
LHL
X2
2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Data In
Write2
Active
LH
HL
Data Out
Read
Active
L
H
High Z
Active
Capacitance1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
CIN
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
I/O Capacitance
CI/O
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
Control
Logic
Page
Decode
Logic
Address
Inputs
A4 - A16
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
Address
Word
Decode
Logic
Address
Inputs
A0 - A3
8K Page
x 16 word
x 8 bit
RAM Array
W
ord
Mux
CE1
CE2
WE
OE
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