參數(shù)資料
型號: MX26F128J3
廠商: Electronic Theatre Controls, Inc.
英文描述: Macronix NBit TM Memory Family 128M [x8/x16] SINGLE 3V PAGE MODE eLiteFlash TM MEMORY
中文描述: 旺宏NBit商標家庭128M的內存[x8/x16]單3V頁模式eLiteFlash商標記憶
文件頁數(shù): 22/47頁
文件大?。?/td> 439K
代理商: MX26F128J3
22
P/N:PM0960
REV. 1.1,OCT. 18, 2004
MX26F128J3
Q7 - Q2 = Reserved
Q1 - Q0 = STS Pin Configuration Codes
00 = default, level mode RY/BY
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high when
the operation indicated by the given configuration is
completed.
Configuration Command Sequences for STS pin
configuration (masking bits Q7- Q 2 to 00h) are as
follows:
Default RY/BY level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
Table 18. Configuration Coding Definitions
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse
width of 250 ns.
Reserved
Pulse on
Program
Complete (1)
bit 1
Pulse on
Erase
Compete (1)
bit 0
bits7-2
Q7 - Q2 are reserved for future use.
default (Q1-Q 0 = 00) RY/BY, level mode
- used to control HOLD to a memory controller to
prevent accessing a eLiteFlash
TM
memory subsystem
while any eLiteFlash
TM
memory device's WSM is busy.
configuration 01 ER INT, pulse mode
- used to generate a system interrupt pulse when any
eLiteFlash
TM
memory device in an array has completed
a Block Erase.
Helpful for reformatting blocks after file system free
space reclamation or "cleanup"
configuration 10 PR INT, pulse mode
-used to generate a system interrupt pulse when any
eLiteFlash
TM
memory device in an array has complete
a Program operation. Provides highest performance for
servicing continuous buffer write operations.
configuration 11 ER/PR INT, pulse mode
-used to generate system interrupts to trigger servic-
ing of eLiteFlash
TM
memory arrays when either erase
or program operations are completed when a common
interrupt service routine is desired.
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