參數(shù)資料
型號: MTW14N50E
廠商: MOTOROLA INC
元件分類: JFETs
英文描述: CONNECTOR ACCESSORY
中文描述: 14 A, 500 V, 0.4 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247AE
文件頁數(shù): 4/8頁
文件大小: 205K
代理商: MTW14N50E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 10) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Low Voltage Capacitance Variation
C
8000
VGS
VDS
Figure 7b. High Voltage Capacitance Variation
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C
0
10
5
0
5
10
15
20
25
10
100
1000
10000
1000
100
10
7000
6000
5000
4000
3000
2000
1000
1
2000
200
20
2
20
200
VDS = 0 V
TJ = 25
°
C
VGS = 0 V
Ciss
Coss
Crss
TJ = 25
°
C
VGS = 0 V
Ciss
Coss
Crss
相關(guān)PDF資料
PDF描述
MTW45N10E TMOS POWER FET 45 AMPERES 100 VOLTS RDS(on) = 0.035 OHM
MTW45N10 TMOS POWER FET 45 AMPERES 100 VOLTS RDS(on) = 0.035 OHM
MTY14N100E TMOS POWER FET 14 AMPERES 1000 VOLTS RDS(on) = 0.80 OHM
MTY14N100 TMOS POWER FET 14 AMPERES 1000 VOLTS RDS(on) = 0.80 OHM
MTY25N60E TMOS POWER FET 25 AMPERES 600 VOLTS RDS(on) = 0.21 OHM
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