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| 型號(hào)： | MTV230M64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Micro Controller with Flash OSD and ISP |
| 中文描述： | 8051嵌入式閃存OSD和ISP的微控制器 |
| 文件頁(yè)數(shù)： | 22/31頁(yè) |
| 文件大?。?/td> | 404K |
| 代理商： | MTV230M64 |
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MTV230M64
Page 22 of 31
Magent
Yellow
White
1
1
1
0
1
1
1
0
1
11.6 Luminance & Border Generator
There are 3 shift registers included in the design which can shift out of luminance and border dots to color
encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will
be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with blackedge for
right and bottom sides only.
11.7 Window Control
The window size and position controls are specified in W1ROW, W1COL, W2ROW, W2COL, W3ROW, W3COL,
W4ROW and W4COL registers. And window 1 has the highest priority, and window 4 has the least, when two
windows are overlapping.
The window shadow width and height controls are specified in WINSW and WINSH registers. And each shadow
has the same priority with its corresponding window.
11.8 OSD Processor registers
Reg name
OSDRA
OSDCA
OSDDT0
OSDDT1
W1ROW
W1COL
W1COL
W2ROW
W2COL
W2COL
W3ROW
W3COL
W3COL
W4ROW
W4COL
W4COL
VERTD
HORD
CH
RSPACE
OSDCON
OSDCON
CHSC
FSSTP
WINSW
WINSH
WINSC
WINSC
XDEL
Addr
FA0h (w)
FA1h (w)
FA2h (w)
FA3h (w)
FC0h (w)
FC1h (w)
FC2h (w)
FC3h (w)
FC4h (w)
FC5h (w)
FC6h (w)
FC7h (w)
FC8h (w)
FC9h (w)
FCAh (w)
FCBh (w)
FCCh (w)
FCDh (w)
FCEh (w)
FD0h (w)
FD1h (r/w) OSDEN
FD2h (r/w)
FD3h (w)
FD4h (w)
FD5h (w)
FD6h (w)
FD7h (w)
FD8h (w)
FD9h (w)
bit7
A1
-
D7
D7
bit6
A0
-
D6
D6
Row start address
Column start address
Column end address
Row start address
Column start address
Column end address
Row start address
Column start address
Column end address
Row start address
Column start address
Column end address
bit5
-
-
D5
D5
bit4
-
C4
D4
D4
bit3
R3
C3
D3
D3
bit2
R2
C2
D2
D2
Row end address
WEN
R
Row end address
WEN
R
Row end address
WEN
R
Row end address
WEN
R
bit1
R1
C1
D1
D1
bit0
R0
C0
D0
D0
WINT
G
WSHD
B
WINT
G
WSHD
B
WINT
G
WSHD
B
-
WSHD
B
G
Vertical delay
Horizontal delay
Character height
-
-
-
-
Row to row spacing
Blend
WENclr
HSP
VSP
CSR
-
FSR
WW21
WW20
WH21
WH20
-
-
-
BSEN
-
Shadow
-
FBEN
DWE
RAMclr
-
CSG
FSG
WW11
WH11
G2
G4
D1
FBKGC
-
CSB
FSB
WW10
WH10
B2
B4
D0
-
FSW
WW41
WH41
-
-
-
-
-
-
WW40
WH40
R1
R3
-
WW31
WH31
G1
G3
-
WW30
WH30
B1
B3
-
R2
R4
D2
OSDRA
(w) :
R3-R0 :This is the row address of the display RAM that next 9-bit data should be written into.
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