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參數(shù)資料
| 型號(hào)： | MTV230M64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Micro Controller with Flash OSD and ISP |
| 中文描述： | 8051嵌入式閃存OSD和ISP的微控制器 |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 404K |
| 代理商： | MTV230M64 |
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MTV230M64
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protocol. There are 2 slave addresses that MTV230M64 can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to 5-
bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI interrupt.
If the matched address is slave A, MTV230M64 will save the matched address's 2 LSB bits to SlvAlsb1 and
SlvAlsb0 register. The data from HSDA is shifted into shift register then written to RCABUF/RCBBUF register
when a data byte is received. The first byte loaded is word address (slave address is dropped). This block also
generates a RCAI/RCBI (receive buffer full interrupt) every time when the RCABUF/RCBBUF is loaded. If S/W
can't read out the RCABUF/RCBBUF in time, the next byte in shift register will not be written to
RCABUF/RCBBUF and the slave block return NACK to the master. This feature guarantees the data integrity of
communication. The WadrA/WadrB flag can tell S/W that if the data in RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into the shift register, resulted in TXABUF/TXBBUF empty
and generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new
byte for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs
every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is cleared
by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control bit ENSCL
is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.3 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by Msel
control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit. The
software program can access the external IIC device through this interface. A summary of master IIC access is
illustrated as follows.
7.3.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV230M64 transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.3.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV230M64 transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV230M64 receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please see the attachments about "Master IIC Receive Timing".
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
addr
bit7
bit6
bit5
bit4
bit3
bit2
MAckO
bit1
P
bit0
S
F00h (r/w)
F01h (r)
F02h (r)
F03h (r)
F03h (w)
F04h (w)
F05h (r/w)
WadrB
MAckIn
TXBI
WadrA
SlvRWB
SAckIn
SLVS
SlvAlsb1 SlvAlsb0
RCBI
SlvBMI
SlvBMI
ESlvBMI
Master IIC receive/transmit data buffer
TXAI
RCAI
SlvAMI
SlvAMI
ESlvAMI
MbufI
MbufI
EMbufI
ETXBI
ERCBI
ETXAI
ERCAI
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