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參數(shù)資料
| 型號： | MTV230M64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Micro Controller with Flash OSD and ISP |
| 中文描述： | 8051嵌入式閃存OSD和ISP的微控制器 |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 404K |
| 代理商： | MTV230M64 |
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MTV230M64
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Mbuf
(w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV230M64's transmission to the IIC bus.
Mbuf
(r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV230M64's receiving from the IIC bus.
RCABUF
(r) :
Slave IIC block A receive data buffer.
TXABUF
(w) :
Slave IIC block A transmit data buffer.
SLVAADR
(w) :Slave IIC block A's enable and address.
ENslvA = 1
→
Enable slave IIC block A.
= 0
→
Disable slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
RCBBUF
(r) :
Slave IIC block B receive data buffer.
TXBBUF
(w) :
Slave IIC block B transmit data buffer.
SLVBADR
(w) :Slave IIC block B's enable and address.
ENslvB = 1
→
Enable slave IIC block B.
= 0
→
Disable slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 2.6V (+/-0.15V) for a specific time, the level triggering LVR will
generate a chip reset signal. After the power supply is above 2.6V (+/-0.15V), LVR maintains in reset state for
144 Xtal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is 0.25
sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer function is
disabled after power on reset, user can activate this function by setting WEN, and clear the timer by set WCLR.
9. A/D converter
The MTV230M64 is equipped with four 6-bit A/D converters, S/W can select the current convert channel by
setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the input
pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage is
greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name
ADC
ADC
WDT
addr
F10h (w)
F10h (r)
F18h (w)
bit7
ENADC
bit6
bit5
bit4
bit3
SADC3
ADC convert Result
bit2
SADC2
bit1
SADC1
bit0
SADC0
WEN
WCLR
WDT2
WDT1
WDT0
WDT
(w) :
Watchdog Timer control register.
= 1
→
Enable WatchDog Timer.
= 1
→
Clear WatchDog Timer.
WDT2: WDT0
= 0
→
overflow interval = 8 x 0.25 sec.
= 1
→
overflow interval = 1 x 0.25 sec.
= 2
→
overflow interval = 2 x 0.25 sec.
= 3
→
overflow interval = 3 x 0.25 sec.
WEN
WCLR
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MTV230MF64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded LCD Monitor Controller with Flash OSD |
| MTV230MS64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded LCD Monitor Controller with Flash OSD |
| MTV230MV64 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded LCD Monitor Controller with Flash OSD |
| MTV2-36PL1 | 制造商:ITT Interconnect Solutions 功能描述:MTV2-36PL1 - Bulk |
| MTV2-36SL1 | 制造商:ITT Interconnect Solutions 功能描述:MTV2-36SL1 - Bulk |
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