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參數(shù)資料
| 型號： | MTV230M64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Micro Controller with Flash OSD and ISP |
| 中文描述： | 8051嵌入式閃存OSD和ISP的微控制器 |
| 文件頁數(shù)： | 11/31頁 |
| 文件大?。?/td> | 404K |
| 代理商： | MTV230M64 |
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MTV230M64
Page 11 of 31
VCNTL
HVCTR0
HVCTR3
HVCTR4
INTFLG
INTEN
F44h (r)
F40h (w)
F43h (w)
F44h (w)
F48h (r/w) HPRchg VPRchg HPLchg
F49h (w)
EHPR
VF7
C1
VF6
C0
CLPEG
VF5
NoHins
CLPPO
VF4
VF3
VF2
VF1
HBpl
VF0
VBpl
CLPW2
CLPW1
CLPW0
DF
VPLchg
EVPL
HFchg
EHF
VFchg
EVF
Vsync
EVsync
EVPR
EHPL
HVSTUS
(r) :
The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1
→
The extracted CVSYNC is present.
= 0
→
The extracted CVSYNC is not present.
Hpol
= 1
→
HSYNC input is positive polarity.
= 0
→
HSYNC input is negative polarity.
Vpol
= 1
→
VSYNC (CVSYNC) is positive polarity.
= 0
→
VSYNC (CVSYNC) is negative polarity.
Hpre
= 1
→
HSYNC input is present.
= 0
→
HSYNC input is not present.
Vpre
= 1
→
VSYNC input is present.
= 0
→
VSYNC input is not present.
Hoff*
= 1
→
HSYNC input's off level is high.
= 0
→
HSYNC input's off level is low.
Voff*
= 1
→
VSYNC input's off level is high.
= 0
→
VSYNC input's off level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH
(r) :
H-Freq counter's high bits.
= 1
→
H-Freq counter is overflow, this bit is clear by H/W when condition removed.
HF13 - HF8 :
6 high bits of H-Freq counter.
Hovf
HCNTL
(r) :
H-Freq counter's low byte.
VCNTH
(r) :
V-Freq counter's high bits.
= 1
→
V-Freq counter is overflow, this bit is clear by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
Vovf
VCNTL
(r) :
V-Freq counter's low byte.
HVCTR0
(w) : H/V SYNC processor control register 0.
C1, C0 = 1,1
→
Select CVSYNC as the polarity, freq and VBLANK source.
= 1,0
→
Select VSYNC as the polarity, freq and VBLANK source.
= 0,0
→
Disable composite function.
= 0,1
→
H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1
→
HBLANK has no insert pulse in composite mode.
= 0
→
HBLANK has insert pulse in composite mode.
HBpl
= 1
→
negative polarity HBLANK output.
= 0
→
positive polarity HBLANK output.
VBpl
= 1
→
negative polarity VBLANK output.
= 0
→
positive polarity VBLANK output.
HVCTR3
(w) :
HSYNC clamp pulse control register.
CLPEG = 1
→
Clamp pulse follows HSYNC leading edge.
= 0
→
Clamp pulse follows HSYNC trailing edge.
CLPPO = 1
→
Positive polarity clamp pulse output.
= 0
→
Negative polarity clamp pulse output.
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